对特权FPGA控制ADC TLC549逻辑代码疑问

在学习《SF-CY3 FPGA套件开发指南Ver7.20 （by特权同学）.pdf》，第6.6 逻辑（Verilog）实例7——基于In-System Sources and Probes Editor的AD采集一节时，对其中的一段代码不是很理解，希望大家帮帮忙，在下不胜感激。

module tlc549(
clk,rst_n,
adc_data,adc_cs_n,adc_clk
);

input clk; //25MHz
input rst_n;
input adc_data;
output adc_cs_n;
output adc_clk;


/************************* 50分频计数 *********************************/

reg[5:0] cntus; //2us

always@(posedge clk or negedge rst_n)
if(!rst_n)
cntus <= 6'd0;
else if((cntus < 6'd49)&&(cstate != IDLE))
cntus <= cntus + 1'b1;
else cntus <= 6'd0;

wire dchag_flag = (cntus == 6'd0); //ADC时钟下降沿标志位，高有效1个时钟周期
wire dlock_flag = (cntus == 6'd24); //ADC时钟上升沿标志位，高有效1个时钟周期

/************************************************************************/

parameter IDLE =3'd0,
TSUDL =3'd1,
START =3'd2,
DTRAN =3'd3,
STOP =3'd4,
TWHDL =3'd5;

reg[2:0] bitnum; //采样数据位寄存器
reg[4:0] d17uscnt; //两次采集数据读取操作的间隔延时计数器，TLC549 > 17us
reg[7:0] adc_dinr; //模数转换数据寄存器
reg[7:0] adc_dinlock; //模数转换数据寄存器，用于实时串行数据的锁存
reg[2:0] cstate,nstate;

//状态迁移
always@(posedge clk or negedge rst_n)
if(!rst_n)
cstate <= IDLE;
else
cstate <= nstate;

//数据采集位的控制，用于准确定位当前采样的ADC数据位
always@(posedge clk or negedge rst_n)
if(!rst_n)
bitnum <= 3'd0;
else if(nstate == IDLE)
bitnum <= 3'd7;
else if((nstate == DTRAN)&&dlock_flag)
bitnum <= bitnum - 1'b1;

//两次读取操作的间隔延时计数逻辑
always@(posedge clk or negedge rst_n)
if(!rst_n)
d17uscnt <= 5'd0;
else if((nstate == TWHDL)&&dchag_flag)
d17uscnt <= d17uscnt + 1'b1;
else if(nstate == IDLE)
d17uscnt <= 5'd0;

//定时ADC读取操作状态控制
always@(cstate or dchag_flag or bitnum or d17uscnt)
case(cstate)
IDLE: nstate <= TSUDL;
TSUDL: if(dchag_flag)
nstate <= START;
else
nstate <= TSUDL;
START: if(dchag_flag)
nstate <= DTRAN;
else
nstate <= START;
DTRAN: if(dchag_flag&&(bitnum == 3'd7))
nstate <= STOP;
else
nstate <= DTRAN;
STOP: if(dchag_flag)
nstate <= TWHDL;
else
nstate <= STOP;
TWHDL: if(dchag_flag&&(d17uscnt == 5'd18))
nstate <= IDLE;
else
nstate <=TWHDL;
default: nstate <= IDLE;
endcase

//数据逐位锁存
always@(posedge clk or negedge rst_n)
if(!rst_n)
adc_dinlock <= 8'h00;
else if((nstate == DTRAN)&&dlock_flag)
adc_dinlock[bitnum] <= adc_data;

//完成1次数据采集后，锁存最新数据
always@(posedge clk or negedge rst_n)
if(!rst_n)
adc_dinr <= 8'h00;
else if(nstate == STOP)
adc_dinr <= adc_dinlock;


assign adc_cs_n = ~((cstate == DTRAN)|(cstate == START)|(cstate == TSUDL));

/************************* ADC时钟产生逻辑 *********************************/
reg adc_clkr; //1MHz

always@(posedge clk or negedge rst_n)
if(!rst_n)
adc_clkr <= 1'b0;
else if((nstate == DTRAN)&&(cntus > 5'd12))
adc_clkr <= 1'b1;
else
adc_clkr <= 1'b0;

assign adc_clk = adc_clkr;
/*******************************************************************************/

//In—System Source and Probes Edi tion例化
mydebug mydebug_inst(
.probe(adc_dinr),
.source()
);



endmodule

以上代码蓝色部分 else if((nstate == DTRAN)&&(cntus > 5'd12))这句如何理解，这个 5'd12这个数值是哪来的？