[问答]

请教verilog中流水线技术的用途？

3655

看到很多资料里说“利用流水线的设计方法，可大大提高系统的工作速度。”

这是一个教材里很常用的例程：

（1）非流水线实现方式

module adder_8bits(din_1, clk, cin, dout, din_2, cout);
input [7:0] din_1;
input clk;
input cin;
output [7:0] dout;
input [7:0] din_2;
output cout;

reg [7:0] dout;
reg cout;

always @(posedge clk) begin
{cout,dout} <= din_1 + din_2 + cin;
endendmodule

（2）2级流水线实现方式：

module adder_4bits_2steps(cin_a, cin_b, cin, clk, cout, sum);
input [7:0] cin_a;
input [7:0] cin_b;
input cin;
input clk;
output cout;
output [7:0] sum;

reg cout;
reg cout_temp;
reg [7:0] sum;
reg [3:0] sum_temp;

always @(posedge clk) begin
         {cout_temp,sum_temp} = cin_a[3:0] + cin_b[3:0] + cin;
end

always @(posedge clk) begin
         {cout,sum} = {{1'b0,cin_a[7:4]} + {1'b0,cin_b[7:4]} + cout_temp, sum_temp};
end

endmodule

注意：这里在always块内只能用阻塞赋值方式，否则会出现逻辑上的错误！

（3）4级流水线实现方式：

module adder_8bits_4steps(cin_a, cin_b, c_in, clk, c_out, sum_out);
input [7:0] cin_a;
input [7:0] cin_b;
input c_in;
input clk;
output c_out;
output [7:0] sum_out;

reg c_out;
reg c_out_t1, c_out_t2, c_out_t3;
reg [7:0] sum_out;
reg [1:0] sum_out_t1;
reg [3:0] sum_out_t2;
reg [5:0] sum_out_t3;

always @(posedge clk) begin
         {c_out_t1, sum_out_t1} = {1'b0, cin_a[1:0]} + {1'b0, cin_b[1:0]} + c_in;
end

always @(posedge clk) begin
         {c_out_t2, sum_out_t2} = {{1'b0, cin_a[3:2]} + {1'b0, cin_b[3:2]} + c_out_t1, sum_out_t1};
end

always @(posedge clk) begin
         {c_out_t3, sum_out_t3} = {{1'b0, cin_a[5:4]} + {1'b0, cin_b[5:4]} + c_out_t2, sum_out_t2};
end

always @(posedge clk) begin
         {c_out, sum_out} = {{1'b0, cin_a[7:6]} + {1'b0, cin_b[7:6]} + c_out_t3, sum_out_t3};
end

endmodule

可是在ISE12.3 下实际时序分析的结果：采用4级流水线比不采用流水线的延时更大：
非流水线方式： timing constraint: TS_clk = PERIOD TIMEGRP "clk" 10 ns HIGH 50%; 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 1.366ns.

4级流水线方式： Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 10 ns HIGH 50%; 10 paths analyzed, 10 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 3.422ns.

采用流水线之后延时更大，意味着系统最高频率更小，工作速度反而降低了，那流水线技术的意义究竟何在？