[讨论]

基于FPGA使用Verilog语言编写TLC5620驱动

2017-11-10 12:59:24 3891 DAC驱动 TLC5620

0 `module TLC5620(clk,reset_n,data,sclk,sdo,ldac,load,ena,done); input clk; //系统输入50MHz晶振 input reset_n; //系统复位时钟 input [10:0]data; //待发送至从器件的11位命令数据 output reg sclk; //串行输出时钟 output reg sdo; //串行输出数据信号线 output reg ldac; //数据更新信号一直低有效 output reg load; //dac装换数据加载信号低脉冲有效 input ena; //模块启动信号，高脉冲有效 output reg done; //完成一次数值更新标志，一个高脉冲，顶层可以检测该信号的下降沿，来控制ena产生上升沿来开启新的数据发送 reg ena1,ena2; //滤波检测ena信号 wire enaPos; wire TLC5620clk; //时钟信号 PLL u1 ( .inclk0(clk), .c0(TLC5620clk)); always@(posedge clk) begin if(!reset_n) begin ena1 <= 1'b0; ena2 <= 1'b0; end else begin ena1 <= ena; ena2 <= ena1; end end assign enaPos = !ena2 && ena1; //检测模块使能上升沿 reg [4:0]index; //过程控制索引值，状态机 reg mouleEna; //用于同步快慢两个时钟触发的进程 always@(posedge clk) begin //时钟50MHz if(!reset_n) mouleEna <= 1'b0; else if(enaPos) mouleEna <= 1'b1; else if(index == 24) //发送完成后关闭继续发送，直到下一次顶层发来的ena高脉冲有效 mouleEna <= 1'b0; end always@(posedge TLC5620clk) begin if(!reset_n) begin index <= 4'd0; ldac <= 1'b0; load <= 1'b1; sclk <= 1'b0; sdo <= 1'b0; end else case(index) //从器件是在下降沿时刻集采数据，故此我们采用在上升沿时刻将数据发出 5'd0: begin sclk <= 1'b0;ldac <= 1'b0;load <= 1'b1;sdo <= 1'b0;done <= 1'b0; if(mouleEna) index <= index + 1'd1; //空闲时刻，等待新的一次数据有效命令来临 end 5'd1: begin sclk <= 1'b1;sdo <= data[10];index <= index + 1'd1; end 5'd2: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd3: begin sclk <= 1'b1;sdo <= data[9];index <= index + 1'd1; end 5'd4: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd5: begin sclk <= 1'b1;sdo <= data[8];index <= index + 1'd1; end 5'd6: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd7: begin sclk <= 1'b1;sdo <= data[7];index <= index + 1'd1; end 5'd8: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd9: begin sclk <= 1'b1;sdo <= data[6];index <= index + 1'd1; end 5'd10: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd11: begin sclk <= 1'b1;sdo <= data[5];index <= index + 1'd1; end 5'd12: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd13: begin sclk <= 1'b1;sdo <= data[4];index <= index + 1'd1; end 5'd14: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd15: begin sclk <= 1'b1;sdo <= data[3];index <= index + 1'd1; end 5'd16: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd17: begin sclk <= 1'b1;sdo <= data[2];index <= index + 1'd1; end 5'd18: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd19: begin sclk <= 1'b1;sdo <= data[1];index <= index + 1'd1; end 5'd20: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd21: begin sclk <= 1'b1;sdo <= data[0];index <= index + 1'd1; end 5'd22: begin sclk <= 1'b0;index <= index + 1'd1; end 5'd23: begin load <= 1'b0;index <=index + 1'd1;done <= 1'b1; end 5'd24: begin index <= 5'd0; end default:; endcase end endmodule 小弟刚入行，如有不对地方还请大神指出。小弟感激 ` TLC5620.zip (3.16 MB, 下载次数: 24 ) 0
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