对SPI0接口的flash进行正常的读写，移植到SPI1上就不行了，请问am335x的SPI0和SPI1有什么不同？

本帖最后由 一只耳朵怪 于 2018-6-5 11:08 编辑

各位高手:
自己做了一块基于AM3352的板子，板上有两个SPI接口，SPI0直接接到一个flash，SPI1接到SPI接口的LCD屏上。目前基于Starterware的例程，在CCS的环境下可以对SPI0接口的flash进行正常的读写，同样的代码，稍微改动后，移植到SPI1上就不行了，用示波器测试发现SPI1的CS0和SPI_CLK都始终为“0”。
我还仔细比较了一下代码运行过程中对SPI0和SPI1的寄存器设置，像MCSPI_CH0CONF, MCSPI_MODULCTRL, MCSPI_CH0STAT, MCSPI_CH0CTRL 这些寄存器都是完全一样的。很想知道AM335X的SPI0和SPI1到底有啥不同。
代码如下：
The problem is that I couldn't find CS0 and SPI_CLK toggling, I copied my code below,

/* Perform Pin-Muxing for SPI1 Instance */
retVal = McSPIPinMuxSetup(1);

/* Enable the clocks for McSPI0 module.*/
McSPI1ModuleClkConfig();
/* Perform Pin-Muxing for CS0 of SPI0 Instance */
retVal = McSPI1CSPinMuxSetup(chNum);
/* Do the necessary set up configura tions for McSPI.*/
McSPISetUp();
ReadSPIDevice();
//////////////////functions///////////////////////
int McSPIPinMuxSetup(unsigned int instanceNum)
[
int status = E_INST_NOT_SUPP;

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_ACLKX) = (CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE |
CONTROL_CONF_MUXMODE(3)); //mode3 for SPI1

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_FSX) = (CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE |
CONTROL_CONF_MUXMODE(3)); //mode3 for SPI1

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AXR0) = (CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE |
CONTROL_CONF_MUXMODE(3)); //mode3 for SPI1


status = S_PASS;
return status;
]
///////////////////////////////////////////////////////////////
void McSPI1ModuleClkConfig(void)
[
HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);
HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);
HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &= ~CM_PER_SPI1_CLKCTRL_MODULEMODE;
HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) |=
CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE;
while((HWREG(SOC_CM_PER_REGS + CM_PER_SPI1_CLKCTRL) &
CM_PER_SPI1_CLKCTRL_MODULEMODE) != CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE);

while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));
while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK)));
]
//////////////////////////////////////////
int McSPI1CSPinMuxSetup(unsigned int csPinNum)
[
int status = E_INVALID_CHIP_SEL;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MCASP0_AHCLKR) = (CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_PUTYPESEL |
CONTROL_CONF_SPI1_SCLK_CONF_SPI1_SCLK_RXACTIVE |
CONTROL_CONF_MUXMODE(3)); //mode3 for SPI1

status = S_PASS;
return status;
]
////////////////////////////////////
//To support SPI1 for LCD, replace the _SPI_0_ with _SPI_1_
static void McSPISetUp(void)
[
/* Reset the McSPI instance.*/
McSPIReset(SOC_SPI_1_REGS);
/* Enable chip select pin.*/
McSPICSEnable(SOC_SPI_1_REGS);
/* Enable master mode of operation.*/
McSPIMasterModeEnable(SOC_SPI_1_REGS);
/* Perform the necessary configuration for master mode.*/
McSPIMasterModeConfig(SOC_SPI_1_REGS, MCSPI_SINGLE_CH,
MCSPI_TX_RX_MODE, MCSPI_DATA_LINE_COMM_MODE_1,
chNum);
/* Configure the McSPI bus clock depending on clock mode. */
McSPIClkConfig(SOC_SPI_1_REGS, MCSPI_IN_CLK, MCSPI_OUT_FREQ, chNum,
MCSPI_CLK_MODE_0);
/* Configure the word length.*/
McSPIWordLengthSet(SOC_SPI_1_REGS, MCSPI_WORD_LENGTH(8), chNum);
/* Set polarity of SPIEN to low.*/
McSPICSPolarityConfig(SOC_SPI_1_REGS, MCSPI_CS_POL_LOW, chNum);
/* Enable the transmitter FIFO of McSPI peripheral.*/
McSPITxFIFOConfig(SOC_SPI_1_REGS, MCSPI_TX_FIFO_ENABLE, chNum);
/* Enable the receiver FIFO of McSPI peripheral.*/
McSPIRxFIFOConfig(SOC_SPI_1_REGS, MCSPI_RX_FIFO_ENABLE, chNum);
]
哪位高手帮忙看看。

谢谢
Chris