对照一下手册看K9K2G16ABA是事满足下面所说的条件:
20.2.5.6.8 Interfacing to a Non-CE Don't Care NAND Flash
As explained in Section 20.2.5.6.4, the EMIFA does not support NAND Flash devices that require the chip
select signal to remain low during the tR time for a read. One way to work around this limitation is to use a
GPIO pin to drive the CE signal of the NAND Flash device. If this work around is implemented, software
will configure the selected GPIO to be low, then begin the NAND Flash operation, starting with the
command phase. Once the
http://processors.wiki.ti.com/index.php/Main_Page
Think Over Before Asking.
http://www.catb.org/~esr/faqs/smart-questions.html#goal