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最近我使用了TMS320F28069PZT做一个系统。今天上机测试样机的时候发现有一路电网采样异常，锁相环不对。观察发现使用的芯片不对，为TMS320F28069FPZT。软件部分在另一台TMS320F28069PZT芯片的样机上正常。有没有哪位用过这两款芯片，并且知道这两款芯片在配置文件上有何不同？
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Arttronix 发表于 2018-8-24 17:48 这是我的cmd文件。同样的程序我放到PZT运行正常，放到FPZT中运行异常。问题是不是在于IQMATH？我看了下文件，还是不知道如果使用FPZT的话，如何修改对应的cmd。 下面是我的cmd文件。 /* // TI File $Revision: /main/3 $ // Checkin $Date: March 3, 2011 13:45:53 $ //########################################################################### // // FILE: F28069.cmd // // TITLE: Linker Command File For F28069 Device // //########################################################################### // $TI Release: F2806x Support Library v140 $ // $Release Date: Fri Oct 17 16:18:59 CDT 2014 $ //########################################################################### */ /* ====================================================== // For Code Composer Studio V2.2 and later // --------------------------------------- // In addition to this memory linker command file, // add the header linker command file directly to the project. // The header linker command file is required to link the // peripheral structures to the proper locations within // the memory map. // // The header linker files are found in // // For BIOS applications add: F2806x_Headers_BIOS.cmd // For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd ========================================================= */ /* ====================================================== // For Code Composer Studio prior to V2.2 // -------------------------------------- // 1) Use one of the following -l statements to include the // header linker command file in the project. The header linker // file is required to link the peripheral structures to the proper // locations within the memory map */ /* Uncomment this line to include file only for non-BIOS applications */ /* -l F2806x_Headers_nonBIOS.cmd */ /* Uncomment this line to include file only for BIOS applications */ /* -l F2806x_Headers_BIOS.cmd */ /* 2) In your project add the path to library search path under project->build options, linker tab, library search path (-i). /*========================================================= */ /* Define the memory block start/length for the F2806x PAGE 0 will be used to organize program sections PAGE 1 will be used to organize data sections Notes: Memory blocks on F28069 are uniform (ie same physical memory) in both PAGE 0 and PAGE 1. That is the same memory region should not be defined for both PAGE 0 and PAGE 1. Doing so will result in corruption of program and/or data. Contiguous SARAM memory blocks can be combined if required to create a larger memory block. */ MEMORY [ PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */ RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */ OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */ FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */ FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */ FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */ FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */ FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */ FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */ CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */ IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */ IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */ IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */ ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */ RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ /* Registers remain on PAGE1 */ BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */ RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */ RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */ RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */ RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */ RAML7 : origin = 0x010000, length = 0x004000 /* on-chip RAM block L7 */ //RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */ USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */ FLASHC : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */ ] /* Allocate sections to memory blocks. Note: codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code execution when booting to flash ramfuncs user defined section to store functions that will be copied from Flash into RAM */ SECTIONS [ /* Allocate program areas: */ .cinit : > FLASHC, PAGE = 0 // .pinit : > FLASHA, PAGE = 0 .text : > FLASHA, PAGE = 0 codestart : > BEGIN, PAGE = 0 ramfuncs : LOAD = FLASHD, RUN = RAML0, LOAD_START(_RamfuncsLoadStart), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), LOAD_SIZE(_RamfuncsLoadSize), PAGE = 0 csmpasswds : > CSM_PWL_P0, PAGE = 0 csm_rsvd : > CSM_RSVD, PAGE = 0 /* Allocate uninitalized data sections: */ .stack : > RAMM0, PAGE = 1 .ebss : > RAML7, PAGE = 1 // RAML2->RAML4 .esysmem : > RAML5, PAGE = 1 // RAML2->RAML4 /* Initalized sections to go in Flash */ /* For SDFlash to program these, they must be allocated to page 0 */ .econst : > FLASHA, PAGE = 0 .switch : > FLASHA, PAGE = 0 /* Allocate IQ math areas: */ IQmath : > FLASHA, PAGE = 0 /* Math Code */ IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD /* Allocate FPU math areas: */ FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD DMARAML5 : > RAML5, PAGE = 1 DMARAML6 : > RAML6, PAGE = 1 DMARAML7 : > RAML7, PAGE = 1 // DMARAML8 : > RAML8, PAGE = 1 /* Uncomment the section below if calling the IQNexp() or IQexp() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD [ IQmath.lib ] */ /* Uncomment the section below if calling the IQNasin() or IQasin() functions from the IQMath.lib library in order to utilize the relevant IQ Math table in Boot ROM (This saves space and Boot ROM is 1 wait-state). If this section is not uncommented, IQmathTables2 will be loaded into other memory (SARAM, Flash, etc.) and will take up space, but 0 wait-state is possible. */ /* IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD [ IQmath.lib ] */ /* .reset is a standard section used by the compiler. It contains the */ /* the address of the start of _c_int00 for C Code. /* /* When using the boot ROM this section and the CPU vector */ /* table is not needed. Thus the default type is set here to */ /* DSECT */ .reset : > RESET, PAGE = 0, TYPE = DSECT vectors : > VECTORS, PAGE = 0, TYPE = DSECT ] /* //=========================================================================== // End of file. //=========================================================================== */ |
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60user19 发表于 2018-8-24 17:59 Simply download motorware and you can find the appropriate cmd file here: C:timotorwaremotorware_x_xx_xx_xxswideccscmdf2802x |
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