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您好！我在使用ad9361 FDD模式双口CMOS全双工1T1R。 通过FPGA读ENSM始终在alert状态，不能进入FDD，同时BBP不能收到data和frame，但是有rx_clk。我用enable脉冲使能一次，然后再使能第二次，也没有进入FDD flush状态。请问需要配置哪些寄存器才能正常进入FDD数据收发状态？能提供一个完整的寄存器配置顺序和参数吗？我晶振是40MHz的，要实现1T1R，双口全双工，我的目的是先能输出100MHz~1300MHz的点频，方式可以采用管脚控制收发，也可以SPI方式控制。后续再改成2T2R独立收发的方式。
我的也是这样的情况：AD9361采用FDD同时收发，ENABLE脉冲触发方式，脉冲宽度为2个FB_CLK时钟，但是读取的0x017的值一直是5，也就是ENSM一直处在ALERT状态。请问该怎么处理？我是用的这个方法：首先已确保0x014[4]=1. 0x013[0] = 1，同时使用SPI语句SPIWrite 0x014=0x23 将状态转入FDD的方法，但是读取的0x017的值一直是5，也就是ENSM一直处在ALERT状态没有进入FDD。SPIWrite 0x014=0x23 后，给ENABLE一个脉冲，进入ALERT状态，再给一个脉冲，进入FDD，读取状态值，发现并没有进入FDD flush状态。 
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qinghong325 发表于 2018-9-10 12:25 谢谢！那些资料我之前都看过了。 我用的FPGA纯逻辑对ad9361进行参数配置，参考时钟是40M无源晶振。我需要设置RF LO 100MHz,ADC和DAC与BBP的接口速率都是30.72MHz,DDR速率，FDD,1T1R,CMOS,DDR,full duplex,enable pulse mode。 我目前遇到的问题是:
can you offer a detail register map that can fit for my application? I use register map as follows: //************************************************************ // AD9361 R2 Auto Generated Initialization Script: This script was // generated using the AD9361 Customer software Version 2.1.3 //************************************************************ // Profile: LTE 20 MHz // REFCLK_IN: 40.000 MHz RESET_FPGA RESET_DUT BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz SPIWrite 3DF,01 // Required for proper operation ReadPartNumber SPIWrite 2A6,0E // Enable Master Bias SPIWrite 2A8,0E // Set Bandgap Trim REFCLK_Scale 40.000000,2,2 // Sets local variables in script engine, user can ignore SPIWrite 292,08 // Set DCXO Coarse Tune[5:0]. Coarse and Fine nominal values used with eval system. Other nominal values may be needed in a customer system SPIWrite 293,80 // Set DCXO Fine Tune [12:5] SPIWrite 294,00 // Set DCXO Fine Tune [4:0] SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 009,07 // Enable Clocks WAIT 20 // waits 20 ms //************************************************************ // Set BBPLL Frequency: 983.040000 //************************************************************ SPIWrite 045,03 // Set BBPLL reflclk scale to REFCLK * 2 SPIWrite 046,02 // Set BBPLL Loop Filter Charge Pump current SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1 SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1 SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2 SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy SPIWrite 043,14 // BBPLL Freq Word (Fractional[7:0]) SPIWrite 042,2E // BBPLL Freq Word (Fractional[15:8]) SPIWrite 041,09 // BBPLL Freq Word (Fractional[23:16]) SPIWrite 044,0C // BBPLL Freq Word (Integer[7:0]) SPIWrite 03F,05 // Start BBPLL Calibration SPIWrite 03F,01 // Clear BBPLL start calibration bit SPIWrite 04C,86 // Increase BBPLL KV and phase margin SPIWrite 04D,01 // Increase BBPLL KV and phase margin SPIWrite 04D,05 // Increase BBPLL KV and phase margin WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 172.800 us (Done when 0x05E[7]==1) SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked) SPIWrite 002,4E // Setup Tx Digital Filters/ Channels SPIWrite 003,5E // Setup Rx Digital Filters/ Channels SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B) SPIWrite 00A,09 // Set BBPLL post divide rate //************************************************************ // AD9361 R2 Auto Generated Initialization Script: This script was // generated using the AD9361 Customer software Version 2.1.3 //************************************************************ // Profile: LTE 20 MHz // REFCLK_IN: 40.000 MHz RESET_FPGA RESET_DUT BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz SPIWrite 3DF,01 // Required for proper operation ReadPartNumber SPIWrite 2A6,0E // Enable Master Bias SPIWrite 2A8,0E // Set Bandgap Trim REFCLK_Scale 40.000000,2,2 // Sets local variables in script engine, user can ignore SPIWrite 292,08 // Set DCXO Coarse Tune[5:0]. Coarse and Fine nominal values used with eval system. Other nominal values may be needed in a customer system SPIWrite 293,80 // Set DCXO Fine Tune [12:5] SPIWrite 294,00 // Set DCXO Fine Tune [4:0] SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2 SPIWrite 009,07 // Enable Clocks WAIT 20 // waits 20 ms //************************************************************ // Set BBPLL Frequency: 983.040000 //************************************************************ SPIWrite 045,03 // Set BBPLL reflclk scale to REFCLK * 2 SPIWrite 046,02 // Set BBPLL Loop Filter Charge Pump current SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1 SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1 SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2 SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy SPIWrite 043,14 // BBPLL Freq Word (Fractional[7:0]) SPIWrite 042,2E // BBPLL Freq Word (Fractional[15:8]) SPIWrite 041,09 // BBPLL Freq Word (Fractional[23:16]) SPIWrite 044,0C // BBPLL Freq Word (Integer[7:0]) SPIWrite 03F,05 // Start BBPLL Calibration SPIWrite 03F,01 // Clear BBPLL start calibration bit SPIWrite 04C,86 // Increase BBPLL KV and phase margin SPIWrite 04D,01 // Increase BBPLL KV and phase margin SPIWrite 04D,05 // Increase BBPLL KV and phase margin WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 172.800 us (Done when 0x05E[7]==1) SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked) SPIWrite 002,4E // Setup Tx Digital Filters/ Channels SPIWrite 003,5E // Setup Rx Digital Filters/ Channels SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B) SPIWrite 00A,09 // Set BBPLL post divide rate //************************************************************ // Setup the Parallel Port (Digital Data Interface) //************************************************************ SPIWrite 010,C8 // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK SPIWrite 011,00 // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data SPIWrite 012,02 // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits SPIWrite 006,00 // PPORT Rx Delay (adjusts Tco Dataclk->Data) SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data) //************************************************************ // Setup RF PLL non-frequency-dependent registers //************************************************************ SPIWrite 261,00 // Set Rx LO Power mode SPIWrite 2A1,00 // Set Tx LO Power mode SPIWrite 248,0B // Enable Rx VCO LDO SPIWrite 288,0B // Enable Tx VCO LDO SPIWrite 246,02 // Set VCO Power down TCF bits SPIWrite 286,02 // Set VCO Power down TCF bits SPIWrite 249,8E // Set VCO cal length SPIWrite 289,8E // Set VCO cal length SPIWrite 23B,80 // Enable Rx VCO cal SPIWrite 27B,80 // Enable Tx VCO cal SPIWrite 243,0D // Set Rx prescaler bias SPIWrite 283,0D // Set Tx prescaler bias SPIWrite 23D,00 // Clear Half VCO cal clock setting SPIWrite 27D,00 // Clear Half VCO cal clock setting SPIWrite 015,0C // Set Dual Synth mode bit SPIWrite 014,15 // Set Force ALERT State bit SPIWrite 013,01 // Set ENSM FDD mode WAIT 1 // waits 1 ms SPIWrite 23D,04 // Start RX CP cal WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1) SPIWrite 27D,04 // Start TX CP cal WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1) SPIWrite 23D,00 // Disable RX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT SPIWrite 27D,00 // Disable TX CP Calibration since the CP Cal start bit is not self-clearing. Only important if the script is run again without restting the DUT //************************************************************ // FDD RX,TX Synth Frequency: 100.000000,100.000000 MHz //************************************************************ //************************************************************ // Setup Rx Frequency-Dependent Syntheisizer Registers //************************************************************ SPIWrite 23A,4A // Set VCO Output level[3:0] SPIWrite 239,C3 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 242,1F // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 238,78 // Set VCO Cal Offset[3:0] SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0] SPIWrite 251,0C // Set VCO Varactor Reference[3:0] SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 23B,92 // Set Synth Loop Filter charge pump current (Icp) SPIWrite 23E,D4 // Set Synth Loop Filter C2 and C1 SPIWrite 23F,DF // Set Synth Loop Filter R1 and C3 SPIWrite 240,09 // Set Synth Loop Filter R3 //************************************************************ // Setup Tx Frequency-Dependent Syntheisizer Registers //************************************************************ SPIWrite 27A,4A // Set VCO Output level[3:0] SPIWrite 279,C3 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 282,1F // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 278,78 // Set VCO Cal Offset[3:0] SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0] SPIWrite 291,0C // Set VCO Varactor Reference[3:0] SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] SPIWrite 27B,92 // Set Synth Loop Filter charge pump current (Icp) SPIWrite 27E,D4 // Set Synth Loop Filter C2 and C1 SPIWrite 27F,DF // Set Synth Loop Filter R1 and C3 SPIWrite 280,09 // Set Synth Loop Filter R3 //************************************************************ // Write Rx and Tx Frequency Words //************************************************************ SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0] SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8] SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16] SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8] SPIWrite 231,50 // Write Rx Synth Integer Freq Word[7:0] SPIWrite 005,55 // Set LO divider setting SPIWrite 273,00 // Write Tx Synth Fractional Freq Word[7:0] SPIWrite 274,00 // Write Tx Synth Fractional Freq Word[15:8] SPIWrite 275,00 // Write Tx Synth Fractional Freq Word[22:16] SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8] SPIWrite 271,50 // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal) SPIWrite 005,55 // Set LO divider setting SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked) SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked) |
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楼主：FDD模式下，我SPIWrite 0x014=0x03 后能关闭tx,可是rx仍一直有数据。SPIWrite 0x014=0x23 后，tx打开，rx还是有接收数据，感觉没法控制rx,tx正常。和你的问题可能有雷同，你最后是怎么解决的？
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2019-2-25 16:25:45
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请问楼主解决了吗
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我也是同样的问题，请问楼主解决了吗，我这里写0x014=0x23，写完再读，确实也写进去了，但是状态还是Alert，VCO也都是校准完成了
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