FX3 USB额外字节从GPIF II到FIFO怎么设计

你好，
我使用Quartus和A莉亚10在我的设计中。我想有USB3.0功能的设计，我修改了slavesyncfifo实例。而不是一个环回，数据只是读到GPIF II接口FIFO。从这里，外部控制器可以访问它和流行的值时。但是，我的问题出现在我的项目的编译中。我认为只有HPS和FX3在我的项目中包含的文件，读取工作正常。然而，当我加入其他外设在我设计的，我接受一个或两个额外的字节。通常在末尾读取额外的字节。我可以看到额外的字节发生在使用SignalTap II当FIFO缓冲区。额外的字节通常只是一个零。由于在额外的字节数量的变化将我的计划，我相信这是一个时机的问题。我发现一对夫妇当搜索关于FX3的时机，但没人回答输入定时。还有一个包括SDC文件示例中的项目，但它只包括输出和输入延迟。输入延迟应该用什么值？
同时，加入一些时序约束后，我发现额外的字节不再是零，但似乎是1日，10点，或取决于最后一个字节值发送。让我进一步考虑这是一个时间问题。
谢谢你



以下为原文
Hi,

I am using Quartus and Arria 10 in my design. I want to have USB3.0 func tionality in the design so I modified the slavesyncFIFO example provided. Instead of a loopback, the data is just read into a FIFO from the GPIF II interface. From here, the external controller can access it and POP values when available. However, my problem arises between compiles of my project. I verified that with only the HPS and FX3 files included in my project, the Read works properly. However, when I add the other peripherals in my design, I receive either 1 or 2 extra bytes. Usually the extra byte(s) are read at the end. I can see the extra byte occurs in the FIFO buffer when using SignalTap II. The extra byte is usually just a zero. Due to the change in the amount of extra byte between compiles of my project, I am led to believe that it is a timing issue. I found a couple when Googling about FX3 timing, but none of them answered input timing. There is also an included SDC file in the example project, but it only includes output and not input delay. What values should I use for the input delay?
Also, after adding some timing constraints, I found that the extra byte was no longer zero, but seemed to either be 01, 10, or 00 depending on the last Byte value sent. I am let further by this to think it is a timing problem.

Thank you