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嗨，那里。我正在阅读中系列MCU家庭手册，研究硬件如何执行I/O功能。我想不出这是怎么回事，请告诉我，THX。附件1是典型的I/O端口的图。场景1：输出高（附件2）。TrIS＝0；端口＝0；P MOS不应该进行，因为在Vgs上有正电压。那么如何输出1？
以上来自于百度翻译 以下为原文 Hi, there. I'm reading the MidRange MCU Family Manual, and studying how hardware work to perform I/O function. I cannot figure out how this do, please point me out, thx. The attachment 1 is a diagram of typical I/O port. scenario 1: output high(attachment 2). TRIS = 0; PORT = 0; The P mos should not be conducted because there is a positive voltage across Vgs. Then how to output 1? Attached Image(s) 
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我不知道你的意思是“正电压横跨VGS”的门将低，源将是高的，所以晶体管是，所以它工作如预期，拉动引脚到VDD编辑。我只是在你的第二张图中发现，你在所有的TRIS锁存销上都有错误的状态。交换所有的“1”和“0”。我认为你的错误是，你认为写入端口锁存器也写入到TIS锁存器。
以上来自于百度翻译 以下为原文 I'm not sure what you mean by "positive voltage across Vgs" The gate will be low, the source will be high, so the transistor is on, so it works as expected, pulling the pin to VDD. Edit. I just spotted in your second diagram, you have the wrong state on all the TRIS latch pins. Swap all the "1" and "0". I think your mistake is that you thought writing to the PORT latch also writes to the TRIS latch. |
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对于Qub：根据我的“错误图”，OR门输出一个，比如说5V，到PMOS的G，S连接到I/O引脚。Vgs是正的，所以PMOS不会被打开。我不明白。当我执行这个指令：TrIS＝0；这个时钟是TILLATCH，对不对？然后执行这个指令：端口＝1；它使数据总线变为高电平和时钟数据锁存器。为什么我在所有TRIS锁存引脚上都错了？写入端口锁存器是：端口＝1；写入TIS锁存器是：TrIS＝0；对吗？
以上来自于百度翻译 以下为原文 To qub: As per my "wrong diagram", the OR gate is outputting one, let's say 5V, to G of PMOS and S is connected to I/O pin. Vgs is positive so the PMOS will not be turned on. I don't get it. When I perform this instruction: TRIS = 0; This clocks TRIS Latch, right? and then perform this instrcution: PORT = 1; which makes data bus to high and clocks Data Latch. Why I'm wrong with state on all TRIS latch pins? Writing to the PORT latch is: PORT = 1; Writing to the TRIS latch is: TRIS = 0; right? |
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是的。在你这样做之后，Q将是0，而Qbar将是1。你在图示上显示相反的。是的。这只改变了数据锁存器，TIS锁存器保持如上所述。
以上来自于百度翻译 以下为原文 Yes. After you do that, Q will be 0, and Qbar will be 1. You show the opposite on your diagram. Yes. This ONLY changes the data latch. The TRIS latch stays as described above. |
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在TIS FF的D输入时，当它为0时，显示1。这就是为什么TISIS QS是错误的
以上来自于百度翻译 以下为原文 You show a 1 at the D input of tris ff when it should be a 0. That’s why the tris Qs are wrong |
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对于Qub：我知道……我们需要先执行TRIS，然后执行端口。因此，TIS锁存器D首先是0。
以上来自于百度翻译 以下为原文 To qub: I see.... We need to perform TRIS first and then PORT. So, D on the TRIS Latch is 0 in the first place. |
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我认为当他写到数据锁存器时，他已经被D“1”弄糊涂了，但这与先前已经写过的TIS锁存器无关。
以上来自于百度翻译 以下为原文 I think he has got confused with the D being "1" when he writes to the DATA latch, but that is irrelevant for the TRIS latch, which has already been written previously. |
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是的，这正是你的代码所做的。TrIS＝0；将0写入TrIS-LATCH，TnPoT＝1；将1写入数据锁存器。
以上来自于百度翻译 以下为原文 Yes, that is exactly what your code is doing. TRIS = 0; writes 0 to the TRIS latch, then PORT = 1; writes 1 to the DATA latch. |
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对于一些人来说，操作是“一目了然的”。其他人，研究逻辑有点，但没有设计逻辑，可能试图弄清楚图表，从经验中知道如何烧毁的东西工作。有时甚至经验丰富的设计师在试图解释他们所知道的正确结果背后的逻辑时会掉头。（也许这从未发生在你身上，但对我来说。不止一次。也许我们可以在一个真值表中把事情拉到一起，而不是引用“数据锁存器”和“Tri-LATCH”，我将把设备的“Q”输出信号称为DATAYFF（用于数据触发器）和TrISIFF（用于TIS触发器）。触发器输出显示为“Q与一个酒吧超过它”将出现在逻辑方程“不DATAYFF”和“不Trasifff”，分别。这里的交易，包括审查的电路操作：门是Low，Pmos是关的时候，它的大门是高的。NMOS在其栅极为高时，Nmos在其门为Low时关闭。这里I/O引脚状态如何取决于应用于其门的逻辑值：当Pmos断开和Nmos断开时，I/O引脚状态为HI-Z。当Pmos断开时，I/O引脚状态为0，Nmos为ON。当Pmos打开时，I/O引脚状态为1，Nmos断开。如果设计允许Pmos和Nmos同时上场，这将是一件坏事，因为PMOS会试图把它拉高，Nmos会试图同时拉低。从图中得出逻辑方程：PMOS门＝（不是DATAYFF）或TrISIFF NMOS门＝（不是DATAYFF）和（不是TISISIFF）。事业单位数据触发器和TIS触发器的离子，利用图中的逻辑方程式。-------- 0，0，1，1，0，0，1，1，1，1，1，1，0，关闭，Hi-Z 1 0 0。O引脚状态等于数据触发器状态指针到O.P.（和其他可能被这个线程中的一些注释误导的人）：先写入TIS锁存器还是数据锁存器并不重要。输出是一个组合结果，它只取决于两个锁存器的当前状态。DaveFootnote，在第一篇文章的注释图中：与描述相反，看图表并使用我的记号，从数据锁存器和TIS锁存器的逻辑输出。使用DATAYFF＝0和Trasifff＝1。PMOS栅为“1”，NMOS栅为“0”。两个晶体管都断开，并且输出是HI-Z，如Trasifff＝1所预期的那样。
以上来自于百度翻译 以下为原文 For some people, the operation is "obvious at a glance." Others, having studied logic a little but not having ever designed logic, might try to make sense of the diagram, knowing from experience how the blasted things work. Sometimes even experienced designers get turned around when trying to explain the logic behind what they know to be the correct result. (Maybe that has never happened to you, but it has to me. More than once.) Maybe we can pull things together in a truth table. Instead of referring to "Data Latch" and "TRIS Latch," I'm going to refer to the "Q" output signals from the devices as Data_FF (for Data Flip-Flop) and Tris_FF (for TRIS Flip-Flop). Flip-Flop outputs shown as "Q with a Bar over it" will appear in logic equations as "Not Data_FF" and "Not Tris_FF," respectively. Here's the deal, including a review of circuit operation: ======================================================================= Transistor operation: Pmos is On when its Gate is Low, Pmos is Off when its Gate is High. Nmos is On when its Gate is High, Nmos is Off when its Gate is Low. Here is how the I/O pin state depends on the logic values applied to their gates: I/O Pin state is Hi-Z when Pmos is Off and Nmos is Off. I/O Pin state is 0 when Pmos is Off and Nmos is On. I/O Pin state is 1 when Pmos is On and Nmos is Off. If the design ever allowed Pmos and Nmos both to be On at the same time, that would be a Bad Thing since Pmos would be trying to pull it high and Nmos would be trying to pull ot low at the same time! ======================================================================= Logic equations from the diagram: Pmos Gate = (Not Data_FF) OR Tris_FF Nmos Gate = (Not Data_FF) AND (Not Tris_FF) ======================================================================= Truth table shows I/O pin state as a function of the Data Flip-Flop and the TRIS Flip-Flop, using logic equations from the diagram. ======================================================================= Data_FF Tris_FF Pmos Pmos Nmos Nmos I/O Pin State State Gate State Gate State State ----------------------------------------------------------------- 0 0 1 Off 1 On 0 0 1 1 Off 0 Off Hi-Z 1 0 0 On 0 Off 1 1 1 1 Off 0 Off Hi-Z ======================================================================= Operation in words (consistent with the Truth Table and the logic equations): When Tris is '1' I/O pin is Hi-Z When Tris is '0' I/O pin state is equal to the Data Flip-Flop state Note to O.P. (and others who might have been misled by some of the comments in this thread): It doesn't matter whether you write to the TRIS latch first or the Data latch first. The output is a combinatorial result that depends only on the current states of the two latches. Regards, Dave Footnote: In the annotated diagram of the first post: Contrary to the description, looking at the diagram and using my notation, the logic outputs from the Data latch and the TRIS latch indicate that Data_FF = 0 and TRIS_FF = 1. Pmos gate is '1' and Nmos gate is '0'. Both transistors are Off, and the output is Hi-Z, as expected when TRIS_FF = 1. |
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