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赫拉mgt银行是113
我正在使用两个极光ips 64b66b。对于一个ip GTX_X1Y0，另一个GTX_X1Y2。在模拟时，结果很好。在MAP中实现它的实现中的显示错误。 包装：2811 - 定向包装无法遵守用户设计约束（LOC = GTXE2_COMMON_X1Y1），这要求将下面列出的符号组合打包到单个GTXE2_COMMON组件中。定向包不可能，因为：目标组件类型可以 涉及的符号包括：GTXE2_COMMON符号“Source2 / Aurora_2 / src_2_wrapper_i / Src_2_multi_gt_i / gtxe2_common_i”（输出信号= NULL）GTXE2_COMMON符号“Source1 / Aurora_1 / src_1_wrapper_i / Src_1_multi_gt_i / gtxe2_common_i”（输出信号= NULL） 它的解决方案是什么？ 找到附件。 以上来自于谷歌翻译 以下为原文 hera mgt bank is 113 i am using two aurora ips 64b66b .for one ip GTX_X1Y0, another GTX_X1Y2.while simulating ,results are good.Coming to implementation its showing error in implementaion.that in MAP. Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=GTXE2_COMMON_X1Y1) which requires the combination of the symbols listed below to be packed into a single GTXE2_COMMON component. The directed pack was not possible because: The target component type can only contain one fragment. The symbols involved are: GTXE2_COMMON symbol "Source2/Aurora_2/src_2_wrapper_i/Src_2_multi_gt_i/gtxe2_common_i" (Output Signal = NULL) GTXE2_COMMON symbol "Source1/Aurora_1/src_1_wrapper_i/Src_1_multi_gt_i/gtxe2_common_i" (Output Signal = NULL) What is the solution for it? find attachments. 
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9个回答
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你好@ rajuponnaganti
看起来你试图在一个四核中使用两个GTXE2_COMMON块。 您必须使用一个GTXE2_COMMON块，因为您在一个块中使用两个GTX。 谢谢， 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题？ ？ 如果没有，你应该在发布之前。 此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hi @rajuponnaganti It looks like you are trying to use two GTXE2_COMMON blocks in one quad. You have to use one GTXE2_COMMON block since you are using two GTXs from one block. Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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您应该将一个Aurora核心的共享逻辑配置为包含在核心中，并将第二个Aurora核心的共享逻辑配置在示例设计中。技术上，核心中具有共享逻辑的核心称为主，另一个称为从核
。 Master包含公共实例，并向slave提供gtrefclkout。请参阅http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf的“共享逻辑”部分。 有关框图，请参见相同PG的图3-17，其中显示了主站和从站之间的互连。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 You should configure one Aurora core's shared logic to be included within the core and the second Aurora core's shared logic to be included in the example design. Technically, the core with shared logic in the core is called as master and the other is called as slave. Master contains common instantiation in it and provides the gtrefclkout to the slave. Please refer to "Shared Logic" section of http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf Refer to Figure 3-17 of the same PG for block diagram showing the inter-connectivity between master and slave.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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我看到了你的重复帖子-http：//forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/mp/640380#M13011http：//forums.xilinx.com/t5/General-Technical-Discussion/problem
-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1 / mp / 640350＃M34780请避免重复发帖。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 I saw duplicate posts from you- http://forums.xilinx.com/t5/Implementation/QPLL-loc-constraints/m-p/640380#M13011 http://forums.xilinx.com/t5/General-Technical-Discussion/problem-in-using-two-GTX-Transceivers-X1Y0-and-X1Y1/m-p/640350#M34780 Please avoid duplicate posts.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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我不是在使用vivado。
我正在使用ise 14.7，设备xc7vx485tboard vc707 以上来自于谷歌翻译 以下为原文 i am not using vivado. i am using ise 14.7, device xc7vx485t board vc707 |
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不建议将ISE生成的Auroa核心与7系列设备一起使用。
请参考http://www.xilinx.com/support/answers/54146.html您需要在Vivado-1中生成两个内核。 Aurora 6466b核心，共享逻辑存在于核心（Master）.2。 示例设计中存在具有共享逻辑的Aurora 64b66b内核（Slave）。然后，您必须在ISE设计中实例化它们并连接http://www.xilinx.com/support/documentation图3-17中所示的时钟信号。 Master to Slave的/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf。试试这个，如果你发现任何问题请告诉我。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 It is not recommended to use ISE generated Auroa core with 7-series devices. Please refer to http://www.xilinx.com/support/answers/54146.html You need to generate two cores in Vivado- 1. Aurora 6466b core with Shared logic present in the core (Master). 2. Aurora 64b66b core with Shared logic present in the example design (Slave). Then you have to instantiate them in your ISE design and connect the clock signals shown under Figure 3-17 of http://www.xilinx.com/support/documentation/ip_documentation/aurora_64b66b/v10_0/pg074-aurora-64b66b.pdf of Master to Slave. Try this and let me know if you see any issues.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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正如你的建议，我创建了一个vivado项目并在流媒体中添加了两个ips。
我找不到任何四元选择aoption。 如图所示。您可以共享vivado的设计文件。 我对vivado很新。 而且我不了解vivado中极光示例设计中的重置逻辑。 需要指导？ 以上来自于谷歌翻译 以下为原文 as you suggested, i created project an vivado and added two ips in streaming. i couldn't find any quad selection aoption. as shown in images.can you share deign files for vivado. i am very new to vivado. and i dibn't understand reset logic in aurora example design in vivado. need guidance? |
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常见的是Aurora核心的一部分，它在核心中具有共享逻辑。
如果在设计中打开master core-aurora_64b66b_0的项目目录，则会找到名称为design_1_aurora_64b66b_0_0_support.v的文件，您可以在其中找到GTHE2_COMMON实例。您的连接看起来是正确的。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 The common is part of the Aurora core which has shared logic present in the core. If you open the project directory of the master core-aurora_64b66b_0 in your design, you will find a file by name design_1_aurora_64b66b_0_0_support.v in which you can find GTHE2_COMMON instantiation. Your connections looks correct.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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我在创建框图中创建了上面的项目。
如何将帧生成模块和ll添加到axi，axi到ll模块极光IPS。 以上来自于谷歌翻译 以下为原文 I created above project in create block diagram. How to add frame gen module and ll to axi,axi to ll module aurora IPS.? |
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您需要为此程序框图生成包装器文件，然后将此包装器与frame_gen / frame_check模块一起添加到设计的顶层。您应该将此包装器文件视为Aurora核心顶级文件，并将其包含在您的设计中
。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题，请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 You need to generate the wrapper file for this block diagram and then add this wrapper along with frame_gen/frame_check modules in the top-level of the design. You should treat this wrapper file as Aurora core top-level file and include this in your design.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
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