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嗨，
我正在使用xilinx 12.1进行设计，我面临一个奇怪的问题。 我之前从未遇到过这种问题所以我需要你们的帮助。 问题是，当我在设计中插入芯片内核生成我的比特流并编程我的FPGA时，编程失败说“DONE没有变高”，而当我拿出芯片内核或来自内核的一些信号时，编程成功 但之后我的JTAG停止工作。 如果我尝试在iMPACT中初始化JTAG链，它会询问我是否有此设备的BSDL或BIT文件，或者如果我尝试运行chipcope，它也会发出警告并且无法启动。 我检查了JTAG电压，它们很好。 很少我的设计工作，所以，我有点卡在这里，因为我不能完全调试我的系统。 Bit文件或我的USB驱动程序有什么问题吗？ 我尝试重新安装驱动程序但没有工作。 然后我重新安装xilinx 12.1，仍然是同样的问题。 是否因为FPGA的大小和我们插入的逻辑的复杂性而发生？ 我的意思是，如果FPGA不够大，无法保持逻辑并且非常合适，那么它是否会导致这种行为？ 还有其他人以前遇到过这个问题吗？ 谢谢 Salimbaba 以上来自于谷歌翻译 以下为原文 Hi, i am using xilinx 12.1 for my design and i am facing a weird probelm. I have never faced this kind of problem before so i need some help from you people. The problem is that when i generate my bitstream with a chipscope core inserted in the design and program my FPGA, programming fails saying that "DONE did not go high" whereas when i take out the chipscope core or some signals from the core, programming succeeds but after that my JTAG stops working. If i try ti initialize JTAG chain in iMPACT it asks me whether i have a BSDL or BIT file for this device or if i try to run chipscope,it also gives a warning and doesn't start. I checked the JTAG voltages and they were fine. Rarely does my design work, so, i am kind of stuck here as i cannot debug my system altogether. Is there something wrong with the Bit file or my u*** drivers? I tried reinstalling the drivers but didn't work. Then i reinstalled xilinx 12.1,still same problem. Does it happen because of the size of the FPGA and the complexity of the logic we are inserting in it ? I mean that if the FPGA is not big enough to hold the logic and it's a very tigh fit, can it lead to such behaviour ? Has anyone else faced this issue before ? thanks Salimbaba 
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8个回答
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ChipScope内核没有任何可能导致设备无法配置的内容。
您没有提到您正在使用的FPGA。 发生这种情况时，您是否检查了所有FPGA电源电压？ 如果是这样的结果是什么？ 你是如何恢复系统再次尝试编程的？ ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 There isn't anything with the ChipScope cores that would cause the device to not configure. You did not mention which FPGA you are using. Did you check all of the FPGA supply voltages when this happened? If so what were the results? How did you recover the system to try programming again? ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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嗨mcgett，
我在我的设计中使用了斯巴达3 xc3s4000 FPGA，是的，今天早上检查了电压，vccint从1.25v到720mv编程后变低了。 我的设计是分层的，即它包含我创建的分区，并且编程后vccint变低。 当我使用之前的版本（这是一个平面设计）对FPGA进行编程时，它工作正常并且vccint没有降低。 我不知道为什么它变低了。 它与层次结构设计有什么关系吗？ 谢谢 以上来自于谷歌翻译 以下为原文 Hi mcgett, I am using spartan 3 xc3s4000 FPGA in my design and yeah i checked the voltages this morning and vccint had gone low after programming from 1.25v to 720mv. My design is hierarchical i.e. it contains a partition that i created and vccint went low after programming. When i programmed the FPGA with a previous revision which was a flat design, it worked and vccint didn't go low. I don't know why it went low. Does it have anything to do with hierarchichal design ? Thanks |
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将VCCINT降至1.2V以下是导致问题的根本原因，需要修复此问题。
XC3S4000是一个非常大的设备，如果使用该设备的很大一部分，您可能会超过电源提供的电流。 合成“平面”与“分层”的设计之间应该没有区别。 您是否检查了已放置和已路由的报告文件，以查看两次尝试中使用的资源量是否有任何差异？ ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 Having VCCINT drop below 1.2V is the root cause of your problem and this needs to be fixed. The XC3S4000 is a very large device and if a significant portion of the device is used you may be exceeding the current available from your power supply. There should be no difference between a design that synthesized "flat" versus "hierarchical". Have you examined the placed and routed report files to see if there is any difference in the amount of resources that were used in both attempts? ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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我再次测试了之前的Rev，即扁平设计。
我不知道发生了什么。 我对平面设计进行了测试，我将其标记为确定并继续进行下一步失败，回过头来看到平面设计也失败了。 我的电压调节器可以提供高达2.9A的电压，所以我不认为我的FPGA正在下沉那么大的电流还是它？ 另外告诉我一件事，FPGA的Vccint应该是1.2V，那么为什么当我在FPGA中添加额外的逻辑时，它的电源轨降至720mv？ 以上来自于谷歌翻译 以下为原文 I tested the previous Rev again i.e. the flat design. I don't know what's happening. I tested the flat design, i marked it as ok and moved on to next step which failed, came back and saw that flat design was also failing. my voltage regulator can source upto 2.9A, so i don't think my FPGA is sinking that much current or is it ? Also tell me one thing, FPGA's Vccint is supposed to be 1.2V,then why is that that when i add extra logic into FPGA, its power rail drops to 720mv ? |
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根据您的描述，您的有源设计消耗超过2.9A，因为您使用的是非常大的设备XC3S4000，所以不应该感到惊讶。
当电源不能满足电流负载时，它将降至零或以较低的电压输出，具体取决于实施方案。 在您的情况下，功率供应正在下降到720mV。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 Based on your description your active design is consuming more than 2.9A and this should not be a surprised since you are using a very large device, XC3S4000. When a power supply can not meet the current load it will either drop to zero or output at a lower voltage depending on the implementation. In your case the power supping is dropping down to 720mV. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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嗨mcgett，
我在FPGA函数描述中读到消费者质量FPGA在quiscent条件下吸收400mA电流，那么它应该如何吸收超过2.9A的电流？ 也有可能在优化时，它已经将一些信号连接到GND，并且由于电流下沉已经增加了？ 非常感谢mcgett。 问候 SalimBaba 以上来自于谷歌翻译 以下为原文 Hi mcgett, I read in the FPGA functional descrption that the consumer quality FPGA draws 400mA in quiscent conditions, how is it supposed to draw more than 2.9A then ? Also is it possible that while optimising, it has connected some signal to GND and due to that current sinking has increased? and thanks a lot mcgett. regards SalimBaba |
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你检查过你的PSU实际可以提供2.9A吗？
尝试连接0.5R（2.4A）或1R（1.2A）电阻，电压是否下降？ 以上来自于谷歌翻译 以下为原文 Have you checked your PSU can actually supply 2.9A ? Try connecting a 0.5R ( 2.4A) or 1R ( 1.2A) resistor across it does the voltage drop ? |
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静止状态表示设备何时不运行。
这与设备配置并开始运行后的状态不同。 根据您的帖子，您可以使用影响工具识别和配置设备，并且只有在配置设备并开始操作后才能解决问题。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 The quiescent condition means when the device is not operating. This is not the same condition that will be present after the device has been configured and starts operating. Based on your posts, you are able to use the impact tool to recognize and configure the device and only after the device has been configured and starts operating does your problem happen. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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