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大家好，
我在设计的地点和路线上遇到以下错误： 错误：PhysDesignRules：2053 - 不支持的MMCM_ADV配置。 具有补偿模式ZHOLD的MMCM_ADV comp clock_manager / mmcm_adv_inst的CLKIN2引脚上的信号sig_gpio_i必须由具有时钟功能的IOB驱动。 它引用的信号跟随我设计的顶层： ... signal sig_gpio_i：std_logic_vector（31 downto 0）; signal sig_ext_int：std_logic_vector（7 downto 0）; ... sig_gpio_i（31 downto 12）'0'）; --yields ERROR：PhysDesignRules：2053 ???????? ... sig_ext_int（7 downto 4）'0'）; - 也产生错误：PhysDesignRules：2053 ???????? ... 这里的主要问题是，在我添加了一些用于调试的芯片范围块（IECON和ILA）的那一刻，所有WAS编译都很好（并且正常工作）。 我看不出chipcope的块如何与上面的信号相关（它们不用于驱动任何chipcope的输入）以引起这样的错误。 只评论chipcope的块实例化似乎解决了这个问题。 有没有人知道如何解决这个问题？ 我正在使用ISE 13.1（在Linux 32位上）合成Virtex 6 xc6vlx240t-ff1156-1（在ML605板中）。 非常感谢您的帮助， 蒂亚戈 以上来自于谷歌翻译 以下为原文 Hi all, I'm getting the following error during the place and route of my design: ERROR:PhysDesignRules:2053 - Unsupported MMCM_ADV configuration. The signal sig_gpio_i<31:12><1> on the CLKIN2 pin of MMCM_ADV comp clock_manager/mmcm_adv_inst with COMPENSATION mode ZHOLD must be driven by an IOB that is clock capable. The signals it refers to are following ones in the top level of my design: ... signal sig_gpio_i : std_logic_vector(31 downto 0); signal sig_ext_int : std_logic_vector(7 downto 0); ... sig_gpio_i(31 downto 12) <= (others => '0'); --yields ERROR:PhysDesignRules:2053 ???????? ... sig_ext_int(7 downto 4) <= (others => '0'); --also yields ERROR:PhysDesignRules:2053 ???????? ... The main problem here is that everything WAS compiling just fine (and working) UNTIL the moment I've added some chipscope blocks for debugging(IECON and ILA). I can't see how chipscope's blocks can be related to the signals above (they are not used to drive any of the chipscope's inputs) in order to cause such error. Only commenting out the chipscope's blocks instantiation seems to fix the problem. Does anyone have an idea about how to fix this ? I'm synthesizing for a Virtex 6 xc6vlx240t-ff1156-1 (in a ML605 board) using ISE 13.1 (on Linux 32bits). Thank you very much for any help, Tiago 
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8个回答
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谢谢你的建议。
我已经通过将CLKIN2连接到“虚拟”时钟输入来解决了这个问题。 然而，将相同的时钟输入连接到CLKIN1和CLKIN2都不起作用（它引发了一些错误，我不记得）。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Thanks for the suggestion. I've already solved the problem by connecting CLKIN2 to a "dummy" clock input. Connecting the same clock input to both CLKIN1 and CLKIN2 didn't work however (it threw some error, I don't remember). View solution in original post |
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我不太了解你的设计，但错误本身表明你的MMCM_ADV组件的CLKIN2引脚已经连接到不具备clk能力的sig_gpio_i。
您可以在高级设计中重新验证MMCM_ADV组件的连接。 以上来自于谷歌翻译 以下为原文 I don't know much your design, but the error itself indicates that CLKIN2 pin of your MMCM_ADV component has been connected to sig_gpio_i which is not clk capable. You may reverify the connections of MMCM_ADV component in your high level design. |
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实例化MMCM_ADV的代码由coregen自动生成。
我检查了生成的连接，CLKIN2引脚初始化为0（我的时钟管理器只有一个输入）。 似乎ISE正在对由GND驱动的信号产生某种混淆，但我不知道为什么只有当我在设计中实例化chipcope组件时才会发生这种情况。 也许存在某种可以应用于CLKIN2的约束以避免这种问题。 以上来自于谷歌翻译 以下为原文 The code that instantiates the MMCM_ADV is generated automatically by coregen. I checked the generated connections and the CLKIN2 pin is initialized with 0 (my clock manager have only one input). It seems ISE is making some kind of confusion with signals driven by GND, but I have no idea why this only happens when I instantiate the chipscope components in the design. Maybe there is some kind of constraint that can be applied to CLKIN2 in order to avoid this kind of problem. |
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只有在将chipcope添加到您的设计中之后才会出现此错误，这一点非常奇怪。
我在Coregen中使用时钟向导核心创建了mmcm并提供了HDL代码。 正如您所提到的，我看到MMCM_ADV的CLKIN2引脚连接到零。 作为临时解决方案，我想，如果你将CLKIN2引脚连接到连接到CLKIN1的相同信号，可能会解决问题。 因为它表示CLKINSEL设置为选择主时钟。 所以它不应该导致问题。 我没试过，但它可能会奏效。 以上来自于谷歌翻译 以下为原文 It's very strange that you have this error only after adding chipscope to your design. I created a mmcm using clock wizard core in Coregen and provided the HDL code. As you mentioned, I saw the CLKIN2 pin of MMCM_ADV is connected to zero. As a temporary solution, I thought, if you conncet CLKIN2 pin to the same signal connected to CLKIN1, may solve the problem. Because it's indicated that CLKINSEL is set to select the primary clock. So it shouldn't cause a problem. I didn't try that, but it may work. |
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谢谢你的建议。
我已经通过将CLKIN2连接到“虚拟”时钟输入来解决了这个问题。 然而，将相同的时钟输入连接到CLKIN1和CLKIN2都不起作用（它引发了一些错误，我不记得）。 以上来自于谷歌翻译 以下为原文 Thanks for the suggestion. I've already solved the problem by connecting CLKIN2 to a "dummy" clock input. Connecting the same clock input to both CLKIN1 and CLKIN2 didn't work however (it threw some error, I don't remember). |
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这种解决方法不是必需的。
遇到同样的问题，经过与赛灵思的进一步讨论后，解决方案是： “此错误是由添加到ChipScope输入信号的KEEP约束引起的，以便在网表中更容易看到，或者在FPGA编辑器中更改。可以通过设置XCO参数禁用KEEP约束的生成来解决此错误 disable_save_keep为true，并重新生成ChipScope核心。“ 因此，编辑chipscope_ila.xco，将disable_save_keep更改为true并重新启动ise作业。 而已 ！ 别忘了点击Kudo ;-) 以上来自于谷歌翻译 以下为原文 This workaround is not necessary. With the same kind of problem, and after further discussion with Xilinx, the solution is : "This error is caused by KEEP constraints that are added to ChipScope input signals to make them easier to see in a netlist, or to change in FPGA Editor. This error can be resolved by disabling the generation of the KEEP constraints by setting the XCO parameter disable_save_keep to true, and regenerating the ChipScope core." So, edit chipscope_ila.xco, change disable_save_keep to true and restart ise job. That's it ! Don't forget to click on Kudo ;-) |
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嗯，每次我尝试你的解决方案时，ila.xco文件参数在重新生成核心时都会被写入false。
还有什么需要做的吗？ 谢谢。 以上来自于谷歌翻译 以下为原文 Hmmmm, everytime I try your solution the ila.xco file parameter gets over written to false when re-generating the core. Is there something else that needs to be done? Thanks. |
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你好dpodva，我注意到了类似的问题。
我认为最好在编辑xco文件之前关闭coregen中的项目。 （我想这就是我被搞砸的地方。）在这里，我详细介绍了我采取的步骤： 首先，关闭项目。 打开.xco文件。 更改“CSET disable_save_keep = true”。 保存文件。 从coregen中，选择“文件”>“打开项目”>选择您的项目。 在“Project IP”窗口中，选择您之前配置的核心。 在右侧的“操作”下，选择“重新生成（在当前项目设置下）”。 单击“是”以显示警告。 核心将被重建。 （仔细检查xco文件是否未被原始选项覆盖。） 以上来自于谷歌翻译 以下为原文 Hello dpodva, I noticed a similar issue. I think it's best to close the project in coregen before editing the xco file. (I think that's where I got screwed up.) Here I detail the steps I took: First, close the project. Open the |
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