BUFGMUX出现错误：地点：1108帮助/原因？

你好，
我一直有BUFGMUX资源的位置有问题，给出了Map错误：ERROR：Place：1108（对不起，我没有确切错误的日志，我现在无法重现...叹息
）
有点背景：Spartan 6 XC6SLX45T（FGG484），ISE 13.1。我的VHDL设计使用5个单端时钟输入，其中1个是同步逻辑的主时钟，其他4个时钟中的每一个用于为4个数据信号提供时钟
进入移位寄存器。
时钟信号及其相关引脚如下所示：clk_master_in：AB13 - GCLK0clk_data_1_in：U12 - GCLK2clk_data_2_in：AB11 - GCLK28clk_data_3_in：T12 - GCLK3clk_data_4_in：Y11 - GCLK29
我使用带有适当参数的 tiMESPEC约束约束了所有5个时钟信号，并且Xilinx工具正在使用约束（我过去曾经使用过ucf文件）。
我必须强调一点，clk_data_1 / 2/3 / 4_in仅连接到移位寄存器的时钟端口，即26位的移位寄存器（定制接口）。
该设计还使用位于X0Y0的GTP的单通道PCIe链路。
PCIe信号都被正确约束，并且与先前工作的设计保持不变。
在第一次映射设计时，我得到所有5个时钟输入导致错误：位置：1108。
遗憾的是，我没有记录确切的错误，但它抱怨BUFGMUX的放置并不理想，并且在检查Xilinx文档时，它们位于相关引脚的错误位置。
我检查了我的信号都是使用GCLK引脚，并且Bank 0和2之间没有使用相同BUFGMUX的冲突 - 全部清除。
我做了很多阅读，并认为我可能与PCIe时钟输入和我自己的时钟输入有冲突。
我相信这只有在我的逻辑使用BUFIO2资源时才有效，这似乎是可以想象的，因为4个时钟与移位寄存器一起使用。
我进一步阅读并发现不应该存在冲突，因为与我正在使用的引脚相关联的BUFIO2资源与用于X0Y0的PCIe资源无关。
过了一会儿，我将其中一个输入时钟引脚移到Bank 0 GCLK引脚并获得了相同的错误：放置：1108，尽管BUFGMUX的位置不同。
作为最后一次尝试，我只是在顶级块级别的所有时钟输入上实例化BUFG，我认为这完全是多余的，但是，错误：地点：1108消失了 - 除了clk_data_1_in ...
然后我想，怎么回事，并且为clk_data_1_in实例化了一个IBUFG和一个BUFG（根据没有BUFIO2的SDR时钟输入的文档），错误就消失了......
我有点困惑可能导致错误发生的原因。
我当然不是专家，但在根据Xilinx文档进行检查时，我发现设计没有任何问题。
为了增加更多的混淆，即使在项目清理并使用SVN恢复到原始代码之后，我也无法重现错误。
由于我无法重现错误，我无法发布确切的错误日志 - 抱歉。
我感到非常焦虑，我有一个严重的设计错误，我有点掩饰。
我真的只是想了解我哪里出错了，以及我对时钟资源的理解是完全错误的。
任何人都可以对这种情况有所了解吗？
我想到的一些问题是：显然，我做错了什么？为什么Xilinx工具使用错误的BUFGMUX？为什么实例化所有信号的IBUFG和BUFG可以解决错误？我是否与我的选择有冲突？
引脚/它们的相关资源和PCIe资源？
另外，在BUFGMUX，BUFIO2等位置方面，是否有可能看到Xilinx工具正在使用哪些资源。这本来可以帮助我找到正在发生的事情，因为我可能已经看到了
冲突或者Xilinx工具只是处于奇怪状态并使用了错误的BUFGMUX等。
无论如何，我真的很感激任何建议，我希望我已经给出了我的设计和问题的足够细节。
如果没有，我很抱歉，并会尽快遗漏任何遗漏。
谢谢，-Doug



以下为原文

Hi There,

I have been having a problem with the placement of BUFGMUX resources which were giving the Map error: ERROR:Place:1108 (Sorry I don't have a log of the exact error, and I can't reproduce it now... sigh)

A bit of background:
Spartan 6 XC6SLX45T (FGG484), ISE 13.1.
My VHDL design uses 5 single ended clock inputs, 1 of which is a master clock for the synchronous logic, each of the 4 other clocks are used to clock 4 data signals into shift registers.
The clock signals and their associated pins are listed below:
clk_master_in: AB13 - GCLK0
clk_data_1_in: U12 - GCLK2
clk_data_2_in: AB11 - GCLK28
clk_data_3_in: T12 - GCLK3
clk_data_4_in: Y11 - GCLK29

I have constrained all 5 clock signals using the TIMESPEC constraint with the appropriate parameters, and the constrains were being used by the Xilinx tools (i've had in the past that the ucf files wasn't being used).
I have to stress here, that the clk_data_1/2/3/4_in are ONLY connected to the clock port of a shift register, a 26-bit one at that (bespoke interface).

The design also uses a single lane PCIe link using GTP located at X0Y0. The PCIe signals are all constrained correctly and have remained unchanged from a previously working design.

Upon mapping the design for the first time, I was getting all 5 clock inputs causing an ERROR:Place:1108. Sadly I don't have the exact error logged, but it complained that the placement of the BUFGMUXs were not ideal, and upon checking the Xilinx documentation, they were in the wrong locations for the relevant pins.

I checked that my signals were all using GCLK pins, and that there were no conflicts between Bank 0 and 2 both using the same BUFGMUX - all clear there.

I did a lot of reading and thought I might have a conflict with the PCIe clock inputs and my own clock inputs. I believe this is only valid if my logic was using BUFIO2 resources, which seemed conceivable as 4 of the clocks are used with shift registers. I read further though and found that there shouldn't be a conflict as the BUFIO2 resources associated with the pins I'm using aren't associated with the PCIe resources used for X0Y0.

After a while I moved one of the input clock pins to Bank 0 GCLK pins and got the same ERROR:Place:1108, albeit with different locations of the BUFGMUXs.

As a final stab, I simply instantiated BUFG's on all the clock inputs at the top-block level, which I thought was completely redundant, but behold, the ERROR:Place:1108 was gone - except for clk_data_1_in...

I then thought, what the hell, and instantiated an IBUFG and a BUFG (as per the documentation for SDR clock inputs without BUFIO2) for clk_data_1_in and the error was gone...

I'm a bit confused what could have been causing the errors to occur. I'm certainly no expert, but I couldn't see any issues with my design when checking it against the Xilinx documentation.

To add more confusion, I can't reproduce the errors, even after a project clean and a revert back to the original code using SVN. Due to the fact I cant reproduce the error, I can't post the exact error logs - sorry about that.

I'm feeling quite anxious that I have a serious design fault, that I have somehow covered up. I'm really just looking for a bit of understanding of where I was going wrong and if my understanding of the clocking resources is completely wrong.

Can anyone shed some light on the situation?

A few questions that come to mind are:
Obviously, what was I doing wrong?
Why were the Xilinx tools using the wrong BUFGMUXs?
Why does instantiating IBUFGs and BUFGs for all the signals cure the errors?
Do I have a conflict with my selection of pins/their associated resources and the PCIe resources?

On a side note, is it possible to see which resources the Xilinx tools are using, in terms of the locations of BUFGMUXs, BUFIO2s etc. This would have really helped me find out what was going on, as I might have been able to see conflicts or if the Xilinx tools were just stuck in an odd state and were utilising the wrong BUFGMUXs etc.

Anyway, I really appreciate any advice at all, and I hope I have given sufficient details of my design and issues. If not, I'm sorry and will put any omissions up as soon as possible.
Thanks,
-Doug