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您好，我的名字是Bontor。
我正在尝试在Digilent Atlys板上实现我的HDL设计（fft模块），该板使用Spartan 6作为FPGA内核。 你的电路板提供100 MHz时钟，而我的设计只能以18 MHz运行。 所以我使用DCM coregen模块将时钟降低到18 MHz。 问题是，DCM输出来自BUFG，在我的设计中，时钟信号用于驱动某些多路复用器，作为选择器输入。 当我直接将DCM时钟输出连接到多路复用器选择器输入时，我得到错误：放置：1206，说“全局缓冲器实例，驱动网络，即驱动以下（前30个）非时钟源引脚脱离芯片。 “ 在这个论坛上阅读后，我发现了类似的问题： http://www.xilinx.com/support/answers/35032.htm 解决方案是使用ODDR2实例化（时钟转发技术），其中时钟信号不直接驱动负载引脚，而是充当ODDR2的输入，然后ODDR2的输出用于驱动引脚。 我尝试在我的设计中实现这个，但它失败了，说“ERROR：Pack：2530 - 双数据速率寄存器无法根据需要加入anOLOGIC组件。” 这是明确的，因为我使用ODDR2输出来驱动内部信号而不是输出引脚（我意识到ODDR2输出必须驱动输出引脚来自http://forums.xilinx.com/t5/Virtex-Family-FPGAs/problem-with- ODDR-集团/ TD-p / 105919） 所以，我需要一个关于如何使用DCM模块输出来驱动内部引脚的解决方案（在这种情况下，mux输入）。 是否有类似ODDR2的模块，但输出可用于内部信号？ 我一直试图在过去的7个小时内解决这个问题，请帮助我。 任何帮助将不胜感激。 以上来自于谷歌翻译 以下为原文 Hello my name is Bontor. I am trying to implement my HDL design (fft module) in Digilent Atlys board that use Spartan 6 as FPGA core. Thee board supply 100 MHz clock while my design can only run at 18 MHz. So I use DCM coregen module to reduce the clock to 18 MHz. Problem is, DCM output is from a BUFG, and in my design, the clock signal is used to drive some mux, as selector input. When I straightforwardly connect DCM clock output to the mux selector input, I get the ERROR:Place:1206, saying" the global buffer instance, driving the net, that is driving the following (first 30) non-clock source pins off chip." After reading on this forum, I found similar problem in: http://www.xilinx.com/support/answers/35032.htm The solution is to use ODDR2 instantiation (clock forwarding technique), where the clock signal does not drive the load pin directly, instead act as input to ODDR2, then the output of ODDR2 is used to drive the pin. I tried to implement this in my design, but it failed,, saying "ERROR:Pack:2530 - The dual data rate register failed to join an OLOGIC component as required.". Which is clear because I used the ODDR2 output to drive internal signal instead of an output pin (I realize ODDR2 output must drive output pin from http://forums.xilinx.com/t5/Virt ... DR-bloc/td-p/105919) So, I need a solution on how to use output of DCM module to drive internal pin (in this case, mux input). Is there similar module like ODDR2, but the output can be used in internal signal? I have been trying to solve this in the last 7 hours, please help me. Any help would be greatly appreciated. 
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使用18MHz时钟生成36MHz定时逻辑很尴尬。
在时钟频率为18MHz的系统中生成36MHz信号供内部使用是没有意义的。 为什么要这么做？ 使用36MHz时钟的36MHz逻辑是一个干净的解决方案。 您可以实现以36MHz时钟运行的简单逻辑。 该逻辑将在两个输入之间交替选择，这有效地以36MHz的速率进行时间复用。 这相当于使用18MHz时钟在时钟的交替相位上进行复用。 例： 永远@（posedge Clock36M） 开始 mux_select //切换触发器 mux_out //时间多路复用输入A和B. 结束 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Using an 18MHz clock to generate 36MHz timed logic is awkward. Generating 36MHz signals for internal use in a system clocked at 18MHz does not make sense. Why would you do that? Using a 36MHz clock for 36MHz logic is the clean solution. You can implement simple logic running at 36MHz clock. The logic would alternate selecting between two inputs, which is (effectively) time multiplexing at 36MHz rate. This is equivalent to using a 18MHz clock to multiplex on alternate phases of the clock. example: always @(posedge Clock36M) begin mux_select <= ~mux_select; // toggle flip-flop mux_out <= mux_select ? mux_input_A : mux_input_B; // time multiplex inputs A and B end -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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谢谢你的回复鲍勃。
我这样做是因为我在设计中使用了折叠技术，我希望在正边缘和负边缘使用不同的bfu核心。 我会看看我的设计改变折叠技术的实现，也许使用计数器是一个很好的解决方案？ 另一方面，您是否知道如何在不使用DCM或其他使用BUFG作为缓冲区的资源的情况下降低时钟频率？ 提前致谢 以上来自于谷歌翻译 以下为原文 Thanks for your reply Bob. I do it because i use folding technique in my design and I want different use of a bfu core at positive edge and negative edge. I will look to my design to change implementation of the folding technique, maybe using a counter is a good solution? On the other hand, do you have idea on how to reduce clock frequency without using DCM or other resource that use BUFG as buffer? Thanks in advance |
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我这样做是因为我在设计中使用折叠技术......
我不熟悉术语“折叠技术”。 你介意澄清这个词吗？ ......我希望在正边缘和负边缘使用不同的bfu核心。 如果我理解正确，你有两个类似的逻辑块在一个系统时钟的相反阶段运行。 它是否正确？ 如果这是正确的，块是以18MHz还是36MHz运行？ 还是其他一些频率？ 也许如果您描述了系统时钟（*所有*）以及它们的使用方式，那么提供一两个有用的建议会更容易。 另一方面，您是否知道如何在不使用DCM或其他使用BUFG作为缓冲区的资源的情况下降低时钟频率？ 如果较低的时钟频率与源时钟频率相关的是一些不错的（最好是偶数）整数，则时钟分频的问题就足够了。 否则，PLL或DCM通过应用乘法和除法来解决问题。 至于避免BUFG，这是一项危险（冒险）的努力。 时钟数字逻辑系统需要严格的时钟偏移控制。 无论工作频率如何，太多的时钟偏差都是致命的。 BUFG是缓冲和分配时钟到整个结构的主要手段，具有（基本上）零偏斜。 换句话说，BUFG是你的朋友。 听起来您正在尽最大努力降低设备功耗。 这是正确的评估吗？ - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 I do it because i use folding technique in my design... I am unfamiliar with the term "folding technique". Do you mind clarifying the term? ... and I want different use of a bfu core at positive edge and negative edge. If I understand you correctly, you have two similar logic blocks operating on opposite phases of a single system clock. Is this correct? If this is correct, are the blocks running at 18MHz or 36MHz? Or some other frequency? Perhaps if you described your system clocks (*all* of them) and how they are used, it would be easier to provide a useful suggestion or two. On the other hand, do you have idea on how to reduce clock frequency without using DCM or other resource that use BUFG as buffer? If the lower clock frequency is related to the source clock frequency by some nice (preferably even) integer, the matter of clock division is simple enough. Otherwise, a PLL or DCM solves the problem by applying both multiplication and division. As for avoiding BUFG, this is a dangerous (risky) endeavour. Clocked digital logic systems require tight clock skew control. Too much clock skew is fatal, regardless of operating frequency. BUFG is the primary means of both buffering and distributing clocks to the entire fabric with (essentially) zero skew. In other words, BUFG is your friend. It sounds like you are doing your best to reduce device power consumption. Is this a correct assessment? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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感谢您的答复。
我这样做是因为我在设计中使用折叠技术...... 我不熟悉术语“折叠技术”。 你介意澄清这个词吗？ 我使用术语“折叠”来指代硬件共享。 ......我希望在正边缘和负边缘使用不同的bfu核心。 如果我理解正确，你有两个类似的逻辑块在一个系统时钟的相反阶段运行。 它是否正确？ 是的。在正边缘，我需要bfu（共享硬件）来运行'x'函数，而在neg边缘，我需要运行'y'函数 如果这是正确的，块是以18MHz还是36MHz运行？ 还是其他一些频率？ 是的，它基本上以36 MHz运行 也许如果您描述了系统时钟（*所有*）以及它们的使用方式，那么提供一两个有用的建议会更容易。 基本上我只使用1个系统时钟，这种“半时钟”方法仅用于上面提到的这个特定硬件。 作为解决方案，我正在考虑使用2个时钟。 1个时钟用于一般系统，另一个用于通用时钟的两倍，用于运行1位计数器（计数器替换半时钟方法）。 当此计数器为0时，我使用共享硬件为x函数工作，然后当它为1时，用于y函数。 您如何看待这种双时钟方法？ 我打算用DCM来生成两个时钟 以上来自于谷歌翻译 以下为原文 Thank you for your response. I do it because i use folding technique in my design... I am unfamiliar with the term "folding technique". Do you mind clarifying the term? I use the term "folding" to refer to hardware sharing. ... and I want different use of a bfu core at positive edge and negative edge. If I understand you correctly, you have two similar logic blocks operating on opposite phases of a single system clock. Is this correct? Yes. At positive edge, i need the bfu (the shared hardware) to run for the 'x' function, and on the neg edge, i needit to run for the 'y' function If this is correct, are the blocks running at 18MHz or 36MHz? Or some other frequency? Yeah, it basically running at 36 MHz Perhaps if you described your system clocks (*all* of them) and how they are used, it would be easier to provide a useful suggestion or two. Basically I just use 1 system clock, and this "half clock" approach is only used in this particular hardware I justmentioned above. As a solution, I am thinking of using 2 clock. 1 clock is for general system, and the other, clocked at twice the general clock, is used to run a 1 bit counter (counter replace half clock approach). When this counter is 0, I use the shared hardware to work for x function, then when it is 1, used for y function. What do you think of this double clock approach? I am planning to use DCM to generate both clock |
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您是否考虑过实现一个时钟频率为36MHz的单个硬件模块，在连续周期的“X”和“Y”线程之间交替？
这不仅简化了时序分析，而且将聚合数据路径大小减少了大约一半。 即使您实现了两个并发运行的并行数据路径，两个数据路径也应该在同一个时钟边沿上运行。 你不能做的是在正时钟边沿和负时钟边沿上计时一个数据路径。 Xilinx FPGA中没有硬件结构，可以在多个时钟边沿上进行时钟控制。 您的选项仅限于以频率“F”计时的两个并行数据路径或以频率“2F”计时的单个多线程数据路径。 这听起来像是一个学校项目或论文。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 Have you considered implementing a single hardware block clocked at 36MHz, alternating between 'X' and 'Y' threads on consecutive cycles? Not only does this simplify timing analysis, but it reduces the aggregate datapath size by roughly half. Even if you implement two parallel datapaths operating concurrently, both datapaths should be operating on the same clock edge. What you cannot do is clock a single datapath on both positive and negative clock edges. There is no hardware construct in a Xilinx FPGA which can be clocked on more than a single clock edge. Your options are limited to two parallel datapaths clocked at frequency "F" or a single multi-thread datapath clocked at frequency "2F". This sounds like a school project or thesis. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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您是否考虑过实现一个时钟频率为36MHz的单个硬件模块，在连续周期的“X”和“Y”线程之间交替？
这不仅简化了时序分析，而且将聚合数据路径大小减少了大约一半。 是的，我想我会考虑这种方法。 谢谢你的想法。 这实际上是一个学校项目，并将被提议参加LSI比赛。 以上来自于谷歌翻译 以下为原文 Have you considered implementing a single hardware block clocked at 36MHz, alternating between 'X' and 'Y' threads on consecutive cycles? Not only does this simplify timing analysis, but it reduces the aggregate datapath size by roughly half. Yes, I think I am going to look to that approach. Thank you for your idea. This is actually a school project and going to be proposed to compete in a LSI competition. |
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请告诉我如何实例化ODDR块2删除错误1203？
急切地请给我ans ........ 以上来自于谷歌翻译 以下为原文 please tell me how to instantiate ODDR block 2 remove error 1203? urgently plz give me the ans ........ |
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嗨
请告诉我如何实例化ODDR块以删除斯巴达6中的DCM时钟错误1203 ...... plz紧急给我ans？ 以上来自于谷歌翻译 以下为原文 hi please tell me how to instantiate ODDR block to remov DCM clocking error 1203 in spartan 6......plz urgently give me the ans? |
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嗨
请告诉我如何实例化ODDR块以删除斯巴达6中的DCM时钟错误1203 ...... plz紧急给我ans？ 以上来自于谷歌翻译 以下为原文 hi please tell me how to instantiate ODDR block to remov DCM clocking error 1203 in spartan 6......plz urgently give me the ans? |
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