完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
德赢Vwin官网
论坛|
我将源时钟除以2，然后尝试将其输入DCM（首先通过缓冲区）。
但我得到的错误是我无法解释的： 错误：NgdBuild：455 - 逻辑网络'clk25'有多个驱动程序：块clk25上的引脚Q，类型为FDC，块上的引脚PAD为clk25.PAD，类型为PADERROR：NgdBuild：462 - 输入焊盘网'clk25'驱动多个 缓冲器：块cgate / u_ibuf上的引脚I，类型为IBUF，引脚I上的块clk25_INV_1_o1_INV_0，类型为INVERROR：NgdBuild：924 - 输入焊盘网'clk25'驱动非缓冲原语：块c上的引脚Q，类型为FDC 我还在.bld文件中找到了一些INFO消息，我不明白。 信息：NgdBuild：889 - 在此设计中，Pad net'clk25'未连接到外部端口。 添加了一个新端口'clk25'并连接到该信号。 我只是将时钟分成如下，然后将clk25送入DCM： cg1：进程（clk_src，rst）如果rst ='1'则开始，然后clk25 elsif clk_src'event和clk_src ='1'然后clk25结束if; 结束过程; 以上来自于谷歌翻译 以下为原文 I am dividing my source clock by 2, then trying to feed this into a DCM (through a buffer first). But I get errors which I cannot explain: ERROR:NgdBuild:455 - logical net 'clk25' has multiple driver(s): pin Q on block clk25 with type FDC, pin PAD on block clk25.PAD with type PAD ERROR:NgdBuild:462 - input pad net 'clk25' drives multiple buffers: pin I on block cgate/u_ibuf with type IBUF, pin I on block clk25_INV_1_o1_INV_0 with type INV ERROR:NgdBuild:924 - input pad net 'clk25' is driving non-buffer primitives: pin Q on block clk25 with type FDC I also found some INFO message in the .bld file, which I don't understand. INFO:NgdBuild:889 - Pad net 'clk25' is not connected to an external port in this design. A new port 'clk25' has been added and is connected to this signal. I am simply dividing the clock as below, then feeding clk25 into the DCM: cg1 : process(clk_src, rst) begin if rst = '1' then clk25 <= '0'; elsif clk_src'event and clk_src='1' then clk25 <= not clk25; end if; end process; 
0
|
|
相关推荐
12个回答
|
|
|
这些工具不会通过结构分频器跟随输入时钟时序。
您是否尝试过DCM的“CLKIN_DIVIDE_BY_2”功能？ 您可以使用Core Generator中的时钟向导根据需要配置DCM。 - Gabor 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The tools won't follow the input clock timing through a fabric divider. Have you tried the "CLKIN_DIVIDE_BY_2" feature of the DCM? You might be able to use the clocking wizard from Core Generator to configure the DCM as required. -- GaborView solution in original post |
|
|
|
|
|
这是一个综合问题。
NGDBuild是实现工具流程的第一步，它只是报告由synthisis创建的连接性问题。 以上来自于谷歌翻译 以下为原文 This is a synthesis issue. NGDBuild is the first step of the Implementation Tool flow and it is simply reporting the connectivty idssues created by synthisis. |
|
|
|
|
|
但是，当我查看综合报告时，它表示没有错误。
以上来自于谷歌翻译 以下为原文 But when I look at the synthesis report, it says there is no error. |
|
|
|
|
|
我猜测在设计的其他地方你也有一个IBUF引入外部引脚并使用IBUF将其驱动到网络clk25上。
可以推断出IBUF本身。 如果您的顶级设计有一个名为clk25的输入，那么该工具将推断出IBUF。 你在做什么不是推荐的方法。 使用结构分隔符通常不是一个好主意，我不知道你为什么要在你的DCM前面做一个。 也许你应该告诉我们你想要完成什么，我们可以建议一种使用FPGA中专用时钟资源的方法。 另外请务必告诉我们您使用的是哪种设备。 Avrum 以上来自于谷歌翻译 以下为原文 I am guessing that somewhere else in the design you also have an IBUF that is bringing in an external pin and driving it onto the net clk25 using an IBUF. The IBUF itself may be inferred. If your top level desing has an input named clk25, then the tool will infer the IBUF. What you are doing is not a recommended approach. It is generally not a good idea to use a fabric divider, and I have no idea why you would want to do one in front of your DCM. Maybe you should tell us what you are trying to accomplish, and we can suggest a way that uses the dedicated clocking resources in the FPGA. Also be sure to tell us what kind of device you are using. Avrum |
|
|
|
|
|
你是对的，我有一个导致错误的IBUF。
我现在删除了它。 我正在使用带有50Mhz输入时钟的半导体板，Spartan 3E-1600。 我需要产生的是3个时钟：25Mhz，90度相移25Mhz和50Mhz。 所以我将50M输入分开，然后将输出DCM，clk0，clk90和clk2x。 有没有更好的办法？ 如果我将50Mhz直接馈入输入，我可以将90度相移输出除以2，但我担心会产生偏斜。 以上来自于谷歌翻译 以下为原文 You are right, I had a IBUF which was causing the error. I removed it now. I am using a digilent board, Spartan 3E-1600, with a 50Mhz input clock at the pad. What I need to generate though is 3 clocks: a 25Mhz, a 90 deg phase shifted 25Mhz and a 50Mhz. So I divided the 50M input, then was going to take at the output of DCM, the clk0, clk90 and clk2x. Is there a better way? If I feed the 50Mhz directly into the input, I could maybe divide the 90 deg phase shifted output by 2, but I'm afraid of the skew that will be produced. |
|
|
|
|
|
正如我所说，只要有可能，你应该避免使用织物分隔物。
这些时钟需要什么？ 他们中的任何一个时钟输入接口？ 它们中的任何一个都会产生系统同步的ouptut接口吗？ Spartan-3E DCM的输入可选2分频。 通过将属性CLKIN_DIVIDE_BY_2设置为TRUE来启用它。 我并不是说这是最好的解决方案，但它明显优于使用布料分隔器。 Avrum 以上来自于谷歌翻译 以下为原文 As I said, whenever possible you should avoid a fabric divider. What do you need these clocks for? Do any of them clock input interfaces? Do any of them generate system synchronous ouptut interfaces? The Spartan-3E DCM has an optional divide by 2 on its input. It is enabled by setting the attribute CLKIN_DIVIDE_BY_2 to TRUE. I am not saying this is the best solution, but it is clearly better than using a fabric divider. Avrum |
|
|
|
|
|
如果你没有在90度延迟25 MHz上驱动大量逻辑，那么在50 MHz的下降沿运行它并使用时钟使能将其降至25 MHz可能是有意义的。
那么你只需要一个具有CLK0输出的DCM用于50 MHz，CLK180输出（或仅使用下降沿触发的触发器）来驱动25 MHz 90度时钟，并且CLK_DV输出的分频设置为2.0用于标准25 MHz时钟 。 还有其他方法可以做到这一点，包括使用适当的时钟使能以100 MHz（CLK2x）运行所有内容。 设置时序约束以处理多周期路径会涉及更多，并且需要更多功率。 但是，您不会遇到任何可能导致保持时间违规的时钟域跨越问题。 - Gabor 以上来自于谷歌翻译 以下为原文 If you're not driving a whole lot of logic on the 90 degree delayed 25 MHz, it might make sense to run it on the falling edge of 50 MHz with a clock enable to take it down to 25 MHz. Then you only need one DCM with the CLK0 output for 50 MHz, CLK180 output (or just use falling edge-triggered flops) to drive the 25 MHz 90 degree clock, and the CLK_DV output with divide set to 2.0 for the standard 25 MHz clock. There are other ways to do this including running everything at 100 MHz (CLK2x) with appropriate clock enables. Setting up the timing constraints to handle multi-cycle paths gets a little more involved, and it takes a bit more power. However you wouldn't have any clock domain crossing issues that could give hold time violations. -- Gabor |
|
|
|
|
|
如果我使用时钟启用，我是否需要应用多周期路径约束？
以上来自于谷歌翻译 以下为原文 if I use a clock enable, do I need to apply a multi-cycle path constraint? |
|
|
|
|
|
dtsao1写道：
如果我使用时钟启用，我是否需要应用多周期路径约束？ 您不需要应用多周期约束，但如果您这样做，则可以更轻松地满足时序要求。 例如，如果你在100 MHz上运行并且不应用任何多周期约束，那么从一个触发器到另一个触发器的每条路径都需要满足10 ns的时序，即使路径在25 MHz在同一个enable上启用另一个。 该路径实际上将具有40 ns，并且多周期约束将允许映射，布局和布线工具花费更少的时间来尝试使路径满足不必要的严格10 ns约束。 - Gabor 以上来自于谷歌翻译 以下为原文 dtsao1 wrote:You don't need to apply a multi-cycle constraint, but it makes the timing easier to meet if you do. For example, if you run everyting on 100 MHz and don't apply any multi-cycle constraints, then every path from one flip-flop to another will need to meet 10 ns timing, even if the path goes fom one flop on the 25 MHz enable to another on the same enable. That path actually would have 40 ns and the multi-cycle constraint would allow the map, place, and route tools to spend less time trying to make the path meet the unnecessarily strict 10 ns constraint. -- Gabor |
|
|
|
|
|
感谢您关于使用180°相移50Mhz和时钟使能的建议。
但是，如果我确实在DCM的输入端使用了分频时钟，我发现该工具无法识别或检查某些输出引脚上的时序，其中我已将输出延迟设置为相对于焊盘上的时钟输入（分频为50Mhz） 到25Mhz）。 即使我在导入时钟进入DCM之前将时钟周期定义为25Mhz。 这是避免分频时钟的原因，还是因为我如何约束输出延迟而发生？ 以上来自于谷歌翻译 以下为原文 Thanks for your suggestion about using the 180 phase shifted 50Mhz and clock enable. If I do use the divided clock at the input of the DCM however, I find the tool does not recognize or check timing on some output pins where I have set the Output delay relative the the clock input at the pad (the 50Mhz that is divided to 25Mhz). This is even though I have defined the clock period of the derived clock to 25Mhz, before it enters the DCM. Is this the reason to avoid divided clocks, or is it happening because of how I constrain the output delay? |
|
|
|
|
|
这些工具不会通过结构分频器跟随输入时钟时序。
您是否尝试过DCM的“CLKIN_DIVIDE_BY_2”功能？ 您可以使用Core Generator中的时钟向导根据需要配置DCM。 - Gabor 以上来自于谷歌翻译 以下为原文 The tools won't follow the input clock timing through a fabric divider. Have you tried the "CLKIN_DIVIDE_BY_2" feature of the DCM? You might be able to use the clocking wizard from Core Generator to configure the DCM as required. -- Gabor |
|
|
|
|
|
我还没试过CLKIN_DIVIDE_BY_2。
我现在就试试吧。 因此，使用此功能，输入时钟I馈送为50Mhz，但DCM的所有输出都将其视为输入为25Mhz，是吗？ 我仍然会将CLKIN_PERIOD设置为20 ns（而不是40）？ 以上来自于谷歌翻译 以下为原文 I didn't try the CLKIN_DIVIDE_BY_2 yet. I'll try it now. So with this feature, the input clock I feed is 50Mhz, but all the outputs of the DCM treat it as if the input was 25Mhz, is that right? I would still set CLKIN_PERIOD to 20 ns (not 40)? |
|
|
|
|
只有小组成员才能发言，加入小组>>
2416 浏览 7 评论
2821 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办？
2292 浏览 9 评论
3372 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
2458 浏览 15 评论
有输入，但是LVDS_25的FPGA内部接收不到数据，为什么？
1123浏览 1评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
581浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
447浏览 1评论
2002浏览 0评论
725浏览 0评论
/6 
关注我们的微信
下载发烧友APP
德赢Vwin官网 观察
版权所有 © 湖南华秋数字科技有限公司
德赢Vwin官网 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
4759
评论
淘帖
2550
