1
完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
在比较两种设计时使用什么更实用?
来自地图报告的占用切片或来自综合报告的实际比率 以上来自于谷歌翻译 以下为原文 What is more practical to use in comparing two design? no. of occupied slices from the map report or the actual ratio from synthesis report |
|
相关推荐
7个回答
|
|
合成后的利用率报告是近似值。因此,如果使用地图利用率报告,则比较准确。
有关详细信息,请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_report_device_utilization.htm。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 The utilization report after synthesis is an approximate value. So, if you use the map utilization report, it is accurate for the comparison. Refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_report_device_utilization.htm for details.----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
|
|
|
地图报告包含很多细节,我需要在比较中只使用一个值。
以上来自于谷歌翻译 以下为原文 the map report contains alot of details, i need to use only one value in the comparing. |
|
|
|
eng_6h6awy_sw写道:
地图报告包含很多细节,我需要在比较中只使用一个值。 你究竟在寻找什么? 您是否尝试根据使用的切片(触发器和LUT)数量来比较设计? 如果是,那么您可以使用第一个代码段中突出显示的详细信息进行比较。 如果是没有。 在I / O和其他原语中,您需要考虑第二个片段中存在的报告元素。 -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 eng_6h6awy_sw wrote:What are you exactly looking for? Are you trying to compare the designs based on the number of slices (flipflops & LUTs) used? If yes, then you can use the details highlighted in first snippet for comparison. If it is the no. of I/Os and other primitives, you need to consider the report elements present in second snippet. ----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
|
|
|
但是通过使用没有。
切片寄存器和切片LUT,我怎么能说设计1的复杂度比设计2的复杂度高......倍? 感谢您的关注 以上来自于谷歌翻译 以下为原文 But by using no. of slice registers and slice LUTs, how can i say that comlexity of design 1 is ...... times higher than complexity of design 2? thanks for your interest |
|
|
|
请定义“复杂性”。
您是否试图了解逻辑在设计中的紧密程度? 或者代码功能有多复杂? -------------------------------------------------- ---------------------------------------------请将帖子标记为 如果提供的信息能够回答您的问题/解决您的问题,请“接受为解决方案”。给予您认为有用的帖子。 以上来自于谷歌翻译 以下为原文 Please define "complexity." Are you trying to see how closely the logic is packed in the designs? Or how complicated the code functionality is?----------------------------------------------------------------------------------------------- Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue. Give Kudos to a post which you think is helpful. |
|
|
|
我需要计算两种设计的硬件复杂性。
比如说 设计1的复杂性比设计2高4倍,设计1的频率比设计2高5倍 以上来自于谷歌翻译 以下为原文 I need to calculate the hardware comlexity of the two design. To say for example complexity of design 1 is 4 times higher than design 2 and frequancy of design 1 is 5 times higher than design 2 |
|
|
|
您通过设计使用的元素数量来衡量复杂性。
难点在于FPGA中存在不同类型的元素:寄存器,LUT,DSP,存储器,serdes等。因此复杂度应该是所有这些元素数量的加权函数。 你有责任提出适当的重量。 我建议从这开始:C = 1 * SREG + 1 * LUT + 3 * IO + 20 * RAM36 + 3 * DSP48 + 3 * MMCM。 如果您不同意任何乘数,欢迎您随意更改它们:-) - 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 You are measuring complexity by the number of elements a design uses. The difficulty with that is in an FPGA there different type of elements: registers, LUTs, DSPs, memory, serdes etc. So complexity should be a weighted function of the number of all these elements. It is your responsibility to come up with the proper weights. I would suggest start with this: C = 1*SREG + 1 * LUT + 3*IO + 20 * RAM36 + 3*DSP48 + 3*MMCM. If you disagree with any of the multipliers, you are welcome to change them as you like :-) - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
|
|
|
只有小组成员才能发言,加入小组>>
2416 浏览 7 评论
2821 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2292 浏览 9 评论
3372 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2458 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1119浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
581浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
447浏览 1评论
2002浏览 0评论
725浏览 0评论
小黑屋| 手机版| Archiver| 德赢Vwin官网 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-21 16:27 , Processed in 1.325016 second(s), Total 88, Slave 72 queries .
Powered by 德赢Vwin官网 网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
德赢Vwin官网 观察
版权所有 © 湖南华秋数字科技有限公司
德赢Vwin官网 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号