错误maplib1120

将来自EDK项目的 implementation ddr2_sdram_wrapper ddr2_sdram_wrapper.ucf中的约束复制到PlanAhead项目中的system.ucf。
通过将这三个约束复制到我的system.ucf中，我可以解决MapLib：1120 - IDELAYCTRL错误：
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [0] .idelayctrl0”LOC =“IDELAYCTRL_X0Y6”;
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [1] .idelayctrl0”LOC =“IDELAYCTRL_X0Y2”;
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [2] .idelayctrl0”LOC =“IDELAYCTRL_X0Y1”;
希望这个帮助，
安德烈斯
在原帖中查看解决方案



以下为原文

Copy the constraints from implementationddr2_sdram_wrapper ddr2_sdram_wrapper.ucf from EDK project into system.ucf in PlanAhead project.

By copying these three constraints into my system.ucf I could solve the MapLib:1120- IDELAYCTRL Error:

INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[0].idelayctrl0" LOC = "IDELAYCTRL_X0Y6";
INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[1].idelayctrl0" LOC = "IDELAYCTRL_X0Y2";
INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[2].idelayctrl0" LOC = "IDELAYCTRL_X0Y1";

Hope this help,

Andres
View solution in original post

嗨，从错误看，你的设计中有三个idelayctrl实例化。
当存在多个idelayctrl时，您需要编写iodelay_group约束或对它们有锁定约束。请查看本文http://www.xilinx.com/support/answers/39966.htm以了解如何处理iodelay组。谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,

From the error it looks like you have three idelayctrl instantiated in your design. When there is more than one idelayctrl you need to write iodelay_group constraints or have lock constraints on them.

Check this article http://www.xilinx.com/support/answers/39966.htm to understand how iodelay groups are handled.

Thanks,
Deepika.Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

None


以下为原文

Thanks for your reply,
i think that my problem is in ucf file , that virtex device does not include any signal net connectivity between IDELAYCTRL components and their associatedIODELAY components, but i didn't undertand how to arrive to the best solution
this is my ucf file
# Virtex 5 ML505 Evaluation Platform
Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15 | IOSTANDARD=LVCMOS33;
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20 | IOSTANDARD=LVCMOS33;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin<0> LOC=AK29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_pin<1> LOC=E28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin<0> LOC=AJ29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin<1> LOC=F28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CE_pin<0> LOC=T28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CE_pin<1> LOC=U30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin<0> LOC=L29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CS_n_pin<1> LOC=J29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin LOC=H30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin LOC=E31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_WE_n_pin LOC=K29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<0> LOC=G31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin<1> LOC=J30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<0> LOC=L30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<1> LOC=M30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<2> LOC=N29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<3> LOC=P29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<4> LOC=K31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<5> LOC=L31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<6> LOC=P31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<7> LOC=P30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<8> LOC=M31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<9> LOC=R28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<10> LOC=J31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<11> LOC=R29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_Addr_pin<12> LOC=T31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25 | IOSTANDARD = SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<0> LOC=AA30 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<1> LOC=AK27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<2> LOC=AJ27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<3> LOC=AA31 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<4> LOC=Y29 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<5> LOC=E27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<6> LOC=G28 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin<7> LOC=H27 | IOSTANDARD = DIFF_SSTL18_II;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17 | IOSTANDARD = LVCMOS33 | PERIOD = 30000 ps;
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7 | IOSTANDARD = LVCMOS33 | TIG;
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7 | IOSTANDARD = LVCMOS33;
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6 | IOSTANDARD = LVCMOS33;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC = AH15 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = E9 | IOSTANDARD=LVCMOS33 | PULLUP;
Net sys_clk_pin PERIOD = 20000 ps;


###### DDR2_SDRAM
###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################

# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib_0/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
"TS_sys_clk_pin" * 2;
# MUX select for read data - optional delay on data to account for byte skews
#INST "*/u_usr_rd_0/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS "TS_sys_clk_pin" * 2;
# Calibration/Initialization complete status flag (for PHY logic only)
INST "*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO
FFS "TS_sys_clk_pin" * 2;
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO
FFS "TS_sys_clk_pin" * 2;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib_0/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_sys_clk_pin" * 2;
INST "*/u_phy_calib_0/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_sys_clk_pin" * 2;
INST "*/u_phy_calib_0/gen_cal_rden_dly*.u_ff_cal_rden_dly"
TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
"TS_sys_clk_pin" * 2;
###############################################################################
# DQS Read Postamble Glitch Squelch circuit related constraints
###############################################################################
###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
# 1. Ununsed "N"-side of DQS diff pair I/O
# 2. DM data mask (output only, input side is free for use)
# 3. Any output-only site
###############################################################################
INST "*DDR2_SDRAM*gen_dqs[0].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y56";
INST "*DDR2_SDRAM*gen_dqs[0].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y56";
INST "*DDR2_SDRAM*gen_dqs[1].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y18";
INST "*DDR2_SDRAM*gen_dqs[1].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y18";
INST "*DDR2_SDRAM*gen_dqs[2].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y22";
INST "*DDR2_SDRAM*gen_dqs[2].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y22";
INST "*DDR2_SDRAM*gen_dqs[3].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y60";
INST "*DDR2_SDRAM*gen_dqs[3].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y60";
INST "*DDR2_SDRAM*gen_dqs[4].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
INST "*DDR2_SDRAM*gen_dqs[4].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
INST "*DDR2_SDRAM*gen_dqs[5].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y216";
INST "*DDR2_SDRAM*gen_dqs[5].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y216";
INST "*DDR2_SDRAM*gen_dqs[6].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y220";
INST "*DDR2_SDRAM*gen_dqs[6].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y220";
INST "*DDR2_SDRAM*gen_dqs[7].u_iob_dqs*u_iddr_dq_ce" LOC = "ILOGIC_X0Y222";
INST "*DDR2_SDRAM*gen_dqs[7].u_iob_dqs*u_iodelay_dq_ce" LOC = "IODELAY_X0Y222";
###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path
###############################################################################
INST "*/u_phy_calib_0/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y28;
INST "*/u_phy_calib_0/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y9;
INST "*/u_phy_calib_0/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y11;
INST "*/u_phy_calib_0/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y30;
INST "*/u_phy_calib_0/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y31;
INST "*/u_phy_calib_0/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y108;
INST "*/u_phy_calib_0/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y110;
INST "*/u_phy_calib_0/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y111;
# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# A single number is used for all speed grades - value based on 333MHz.
# This can be relaxed for lower frequencies.
NET "*DDR2_SDRAM*u_phy_io_0*en_dqs*" MAXDELAY = 600 ps;
NET "*DDR2_SDRAM*u_phy_io_0*gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;

###############################################################################
# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
# for DQS Read Postamble Glitch Squelch circuit
###############################################################################
# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
# where slack account for rise-time of DQS on board. For now assume slack =
# 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
# time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*DDR2_SDRA*gen_dqs

.u_iob_dqs*u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*DDR2_SDRAM*gen_dq

.u_iob_dq*gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
###############################################################################
# MIG 2.2: Prevent unrelated logic from being packed into any slices used
# by read data capture RPM's - if unrelated logic gets packed into
# these slices, it could cause the DIRT strings that define the
# IDDR -> fabric flop routing to become unroutable during PAR stage
# (unrelated logic may require routing resources required by the
# DIRT strings - MAP does not currently take into account DIRT
# strings when placing logic
###############################################################################
# AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
################################################################################
#INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y22; # AF30 X0Y22 *
#INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y23; # AK31 X0Y23
#INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y25; # AF31 X0Y25
#INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; # AD30 X0Y26
#INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y21; # AJ30 X0Y21
#INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y22; # AF29 X0Y22 ***
#INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y24; # AD29 X0Y24
#INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y24; # AE29 X0Y24
#INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y8; # AH27 X0Y8 ***
#INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y12; # AF28 X0Y12
#INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y13; # AH28 X0Y13
#INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y14; # AA28 X0Y14
#INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y6; # AG25 X0Y6
#INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y8; # AJ26 X0Y8 *
#INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y13; # AG28 X0Y13
#INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y14; # AB28 X0Y14
#INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y15; # AC28 X0Y15
#INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y16; # AB25 X0Y16 ***
#INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y18; # AC27 X0Y18
#INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y19; # AA26 X0Y19
#INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y16; # AB26 X0Y16 *
#INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y17; # AA24 X0Y17
#INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y18; # AB27 X0Y18
#INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y19; # AA25 X0Y19
#INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; # AC29 X0Y26
#INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y29; # AB30 X0Y29 ***
#INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; # W31 X0Y33
#INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35; # V30 X0Y35
#INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y29; # AC30 X0Y29 *
#INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; # W29 X0Y32
#INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # V27 X0Y34 ***
#INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # W27 X0Y36
#INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; # V29 X0Y32
#INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # Y27 X0Y36
#INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # Y26 X0Y38
#INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # W24 X0Y39
#INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # V28 X0Y34 *
#INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37; # W25 X0Y37
#INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # W26 X0Y38
#INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # V24 X0Y39
#INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y100; # R24 X0Y100
#INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y101; # P25 X0Y101
#INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y102; # N24 X0Y102
#INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y103; # P26 X0Y103
#INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y100; # T24 X0Y100
#INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y101; # N25 X0Y101
#INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y103; # P27 X0Y103
#INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y104; # N28 X0Y104
#INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y104; # M28 X0Y104
#INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y106; # L28 X0Y106
#INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y112; # F25 X0Y112
#INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y113; # H25 X0Y113
#INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y105; # K27 X0Y105
#INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y106; # K28 X0Y106
#INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y113; # H24 X0Y113
#INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y114; # G26 X0Y114
#INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y114; # G25 X0Y114
#INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y116; # M26 X0Y116
#INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y117; # J24 X0Y117
#INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y118; # L26 X0Y118
#INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y115; # J27 X0Y115
#INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y116; # M25 X0Y116
#INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y118; # L25 X0Y118
#INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y119; # L24 X0Y119
if you have any idea help me
thanks again

您好，请尝试编写IODELAY_GROUP约束并将IODELAY元素关联到相应的IODELAY组。请参阅第页的“IDELAYCTRL使用和设计指南”。
可从http://www.xilinx.com/support/documentation/user_guides/ug361.pdf获取的SelectIO资源用户指南中的117个您也可以查看UG 625（http://www.xilinx.com/support/documentation/sw_manuals）
/xilinx14_7/cgd.pdf），指南描述了使用IODELAY_GROUP约束来分组一组IDELAY和IODELAY约束，以便在设计中启用IDELAYCTRL的自动复制和放置。如果问题仍然存在，请附上指定ISE版本的测试用例
正在使用。
问候，阿希什-----------------------------------------------
- - - - - - - - - - - - - - - - - - - - - - - -请注意-
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .--------------------
--------------------------------------------------
------------------------



以下为原文

Hello,

Please try writing IODELAY_GROUP constraints and associate the IODELAY elements to the corresponding IODELAY group.

Check “IDELAYCTRL Usage and Design Guidelines” on page no. 117 of SelectIO Resources User Guide which is available at
http://www.xilinx.com/support/documentation/user_guides/ug361.pdf
You can also check UG 625 (http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf), guide depicts the use of IODELAY_GROUP constraints to group a set of IDELAY and IODELAY constraints to enable automatic replication and placement of IDELAYCTRL in the design.

If the issue still persists, attach the testcase specifying ISE version which you are using.Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

感谢您的回复
不幸的是，我没有找到这个链接的最佳解决方案



以下为原文

Thanks for your reply
unfortunately i didn't found the best solution with this link

嗨，
检查此帖子：http：//forums.xilinx.com/t5/Virtex-Family-FPGAs/idelayctrl-with-iodelay-group-example/td-p/320793，Avrum将简单地解释IODELAY_GROUP用法。
粘贴在这里供您参考。
IODELAY_GROUP将特定的IODELAYCTRL与一堆IODELAY相关联。
只有当IODELAYCTRL对于一堆IODELAY与其他IODELAY不同时，才需要这样做。
如果您的目标是拥有所有IODELAYCTRL
- 由同一时钟（200MHz）提供时钟
- 由相同的复位信号复位
- 只有一个组合就绪信号
那么你不需要指定多个IODELAY_GROUP。
只需实例化一个IODELAYCTRL（没有IODELAY_GROUP）并且不设置IODELAY的IODELAY_GROUP，该工具将自动将一个（并且只有一个）IODELAYCTRL复制到三个所需的库中。
如果你确实想要三个银行中的每一个都有不同的组，那么你会
- 实例化三个IODELAYCTRL，每个IODELAYCTRL具有不同的IODELAY_GROUP
- 对于特定银行中的三个IODELAY中的每一个，我们使用与IODELAYCTRL之一相同的IODELAY_GROUP
- 同一银行中的三个必须使用相同的IODELAY_GROUP
但是再一次 - 这在大多数情况下都不是必需的......只是实例化一个没有IODELAY_GROUP的IODELAYCTRL。
如果您仍然无法弄清楚设计中的用法，请在此处附上您的测试用例。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,

Check this thread http://forums.xilinx.com/t5/Virtex-Family-FPGAs/idelayctrl-with-iodelay-group-example/td-p/320793 the IODELAY_GROUP usage is explained in easy terms by Avrum. Pasting it here for your reference.

The IODELAY_GROUP is to associate a specific IODELAYCTRL with a bunch of IODELAYs. This is only necessary when there is some reason for the IODELAYCTRL for one bunch of IODELAYs to be different from others. If your goal is to have all IODELAYCTRLs
- clocked by the same clock (at 200MHz)
- reset by the same reset signal
- have only a single combined ready signal

then you don't need to specify multiple IODELAY_GROUPs. Simply instantiate one IODELAYCTRL (with no IODELAY_GROUP) and do not set the IODELAY_GROUP of the IODELAYs, and the tool will automatically replicate the one (and only one) IODELAYCTRL into the three required banks.

If you did want a different group for each of the three banks then you would
- instantiate three IODELAYCTRLs each with a different IODELAY_GROUP
- for each of the three IODELAYs in a particular bank, us the same IODELAY_GROUP as one of the IODELAYCTRLs
- the three in the same bank must use the same IODELAY_GROUP

But again - this isn't necessary most of the time... Just instantiate one IODELAYCTRL with no IODELAY_GROUP.

In case if you are still not able to figure out the usage in your design, attach your test case here.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

非常感谢你，
因为我是初学者我这个域我不明白如何在我的ucf文件中实例化这些idelayctrls。



以下为原文

Thank you very much,
Cause i'm a beginner i this domain i didn't understand how to instantiate these idelayctrls in my ucf file.

嗨，
UCF语法如下
INST“instance_name”IODELAY_GROUP = group_name;
您需要使用设计中的IDELAY / IDELAYCTRL实例名称替换实例名称。
您可以通过打开技术原理图找到这些名称。
有关语法帮助，请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf的第-130页。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
---------------------------------------------- Google之前的问题
张贴。
如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）



以下为原文

Hi,

The UCF syntax is as below

INST "instance_name" IODELAY_GROUP = group_name;

You need to replace the instance name with the IDELAY/IDELAYCTRL instance names in the design. You can find these names by opening technology schematic.

You can refer to page-130 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf for syntax help.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

你好，
我将此行添加到ucf文件中
INST“* / u_idelayctrl”IODELAY_GROUP = IODELAY_GRP;
可能system.vhd我补充说
属性IODELAY_GROUP：string;
DDR2_SDRAM的属性IODELAY_GROUP：DDR2_SDRAM是“IODELAY_GRP”;
同样的错误仍然存在



以下为原文

Hello,
i added this line to ucf file
INST "*/u_idelayctrl" IODELAY_GROUP=IODELAY_GRP;
to may system.vhd i added
attribute IODELAY_GROUP: string;
attribute IODELAY_GROUP of DDR2_SDRAM: DDR2_SDRAM is "IODELAY_GRP";
the same error persist

嗨，
如果您在UCF文件中包含IODELAY_GROUP约束，则不需要再次将其包含在.vhd文件中。
为了您的参考，我附加了UCF文件，可以提供对IODELAY_GROUP约束的使用的见解。
在该UCF中，i_idelayctrl是IDELAYCTRL的实例名称，并且各个IODELAY元素的其他实例取自技术原理图。
您可以将其用作设计的参考。
如果您仍然发现任何问题，请附上测试用例以便进一步调试。
问候，阿希什-----------------------------------------------
- - - - - - - - - - - - - - - - - - - - - - - -请注意-
如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。感谢Kudos .--------------------
--------------------------------------------------
------------------------
pipe.ucf 3 KB



以下为原文

Hi,

If you are including IODELAY_GROUP constraints in UCF file, then it is not needed to again include it in your .vhd file.
For your reference, I have attached UCF file which can provide an insight to usage of IODELAY_GROUP constraints.
In that UCF, i_idelayctrl is the instance name of IDELAYCTRL and other instances of individual IODELAY elements are taken from the technology schematic.
You can use it as a reference for your design.
If you still see any issue, please attach test case for further debugging.
Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
---------------------------------------------------------------------------------------------- pipe.ucf ‏3 KB

嗨，
谢谢您的回复
我在我的ucf文件中测试了这些修改，同样的错误仍然存在，我不知道如何解决它。
我想只用EDK翻译我的设计，或修改设计中的一些设计



以下为原文

Hi,
Thank you for your reply
i assayed with these modifications in my ucf file , the same error persists i don't know how to fix it. i think to translate my design in only EDK , or modify some propreties in design

将来自EDK项目的 implementation ddr2_sdram_wrapper ddr2_sdram_wrapper.ucf中的约束复制到PlanAhead项目中的system.ucf。
通过将这三个约束复制到我的system.ucf中，我可以解决MapLib：1120 - IDELAYCTRL错误：
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [0] .idelayctrl0”LOC =“IDELAYCTRL_X0Y6”;
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [1] .idelayctrl0”LOC =“IDELAYCTRL_X0Y2”;
INST“DDR2_SDRAM / * gen_instantiate_idelayctrls [2] .idelayctrl0”LOC =“IDELAYCTRL_X0Y1”;
希望这个帮助，
安德烈斯



以下为原文

Copy the constraints from implementationddr2_sdram_wrapper ddr2_sdram_wrapper.ucf from EDK project into system.ucf in PlanAhead project.

By copying these three constraints into my system.ucf I could solve the MapLib:1120- IDELAYCTRL Error:

INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[0].idelayctrl0" LOC = "IDELAYCTRL_X0Y6";
INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[1].idelayctrl0" LOC = "IDELAYCTRL_X0Y2";
INST "DDR2_SDRAM/*gen_instantiate_idelayctrls[2].idelayctrl0" LOC = "IDELAYCTRL_X0Y1";

Hope this help,

Andres