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至于综合和实现流程中的“编辑时序约束”（见下文），它们是否应该与相同的文件相关？ 我可以保留文件，这些文件将在综合过程中考虑，在实施过程中不予考虑，反之亦然？ 实际上我在合成流的“编辑时序约束”中定义了异步时钟组并且运行完美（当我点击“时钟”菜单中“时钟”菜单下的“设置时钟组”子菜单时，我看到了定义的约束 约束“选项卡”。 但是，当我点击实施流程的“编辑时序约束”时，我在“设置时钟组”子菜单下看不到任何时钟组定义......我是否应该看到与合成流程相同的时钟组定义 ， 我对吗？ 可能发生这种情况是因为其中一个时钟在实现过程中消失了（我收到了这样的警告）并且“set async clock groups”命令变得无效？ 我该如何解决这个问题？ 是否可以为综合和实施流程保留不同的约束文件？ 谢谢！ 以上来自于谷歌翻译 以下为原文 Hi All, As for the "Edit timing Constraints" in the Synthesis and Implementation flow (see below), should they be related to the same files? Can I keep files, which will be considered during synthesis and will not be considered during implementation and vice versa? Actually I defined the asynchronous clock groups in the "Edit Timing Constraints" for Synthesis flow and that runs perfectly (I see the defined constraints when I click on the "Set Clock Groups" sub-menu under the "Clocks" menu in the "Timing Constraints" tab). But, when I click on the "Edit Timing Constraints" for Implementation flow, I don't see any clock groups definitions under the "Set Clock Groups" sub-menu... Should I see the same clock groups definitions as for Synthesis flow, am I right? Probably this happen because one of the clocks disappears during implementation (I received such warning) and the "set async clock groups" command became invalid? How should I solve this issue? Is it possible to keep different constraint files for Synthesis and Implementation flows? Thank you! 
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@ dmitry1417，
是的，您应该看到相同的时钟组用于综合和 实现。 你能检查一下从合成设计中修剪掉的时钟的连接性吗？ 您可以使用两个不同的xdc文件，并为单个xdc文件设置“Used In”属性，如下所示： 请查看以下用户指南中的第83页： http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug895-vivado-system-level-design-entry.pdf#nameddest=xWorkingWithConstraints 如果时钟被修整，则对实现xdc文件应用相同的时钟组约束将发出警告，指出异步时钟组中的指定时钟丢失。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @dmitry1417, Yes, You should see the same clock groups for both synthesis & implementation. Can you check the connectivity of the clock which got trimmed from synthesized design? You can have two different xdc files and set "Used In" properties for the individual xdc file as shown below: Check out page number 83 in the below User guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug895-vivado-system-level-design-entry.pdf#nameddest=xWorkingWithConstraints If the clock is trimmed then applying the same clock group constraint for the implementation xdc file will give a warning that the specified clock in asynchronous clock groups is missing. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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@ dmitry1417，
共享信息是否已回答您的查询？ --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @dmitry1417, Did the shared information answered your query? --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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