7系列收发器时序违规

嗨，如果你作为设计师认为必须分析这条路径（不要将其视为异步路径，因为从相位关系中看起来这看起来不像是相关时钟），那么使用Set_max_delay -datapath_only约束。
通常为了找到这个约束的值，我们需要1个时钟周期的快速时钟。谢谢，Yash
在原帖中查看解决方案



以下为原文

Hi,

If you as a designer thinks this path has to be analyzed (Not to be consider as async path because from the phase relation ship this looks like not related clocks) then use the Set_max_delay -datapath_only constraint. Usually to find the values of this constraint we take 1 clock cycle period of fast clock.

Thanks,
YashView solution in original post

嗨，这是跨时钟域处理问题.Vivado认为所有时钟都是同步的，并考虑用于分析的最差有效边缘关系。
在你的情况下，最坏的可能是0.8ns（设置要求），这似乎不可能满足。你能分享原理图和完整的时间报告吗？谢谢，Yash



以下为原文

Hi,

This is cross clock domain handling issue.
Vivado consider all clocks as synchronous and consider the worst active edge relation for analysis. In your case the worst possible is 0.8ns (requirement for setup), this looks like impossible to meet.

Can you please share the schematic and complete timing report?

Thanks,
Yash

None


以下为原文

Hello @yashp

There is design schematic and detail timing report.


Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.-----------------------------------------------------------------------------------------------------------------------------------------------------| Tool Version : Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016| Date : Tue Jul 4 09:40:43 2017| Host : amd33 running 64-bit Red Hat Enterprise Linux Server release 5.7 (Tikanga)| Command : report_timing_summary -warn_on_violation -max_paths 10 -file GTX_V7_timing_summary_routed.rpt -rpx GTX_V7_timing_summary_routed.rpx| Design : GTX_V7| Device : 7v2000t-flg1925| Speed File : -1 PRODUCTION 1.10 2014-09-11-----------------------------------------------------------------------------------------------------------------------------------------------------Timing Summary Report------------------------------------------------------------------------------------------------| Timer Settings| -------------------------------------------------------------------------------------------------------------- Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing reportTable of Contents-----------------1. checking no_clock2. checking constant_clock3. checking pulse_width_clock4. checking unconstrained_internal_endpoints5. checking no_input_delay6. checking no_output_delay7. checking multiple_clock8. checking generated_clocks9. checking loops10. checking partial_input_delay11. checking partial_output_delay12. checking latch_loops1. checking no_clock-------------------- There are 0 register/latch pins with no clock.2. checking constant_clock-------------------------- There are 0 register/latch pins with constant_clock.3. checking pulse_width_clock----------------------------- There are 0 register/latch pins which need pulse_width check4. checking unconstrained_internal_endpoints-------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock.5. checking no_input_delay-------------------------- There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint.6. checking no_output_delay--------------------------- There are 0 ports with no output delay specified. There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it7. checking multiple_clock-------------------------- There are 0 register/latch pins with multiple clocks.8. checking generated_clocks---------------------------- There are 0 generated clocks that are not connected to a clock source.9. checking loops----------------- There are 0 combinational loops in the design.10. checking partial_input_delay-------------------------------- There are 0 input ports with partial input delay specified.11. checking partial_output_delay--------------------------------- There are 0 ports with partial output delay specified.12. checking latch_loops------------------------ There are 0 combinational latch loops in the design through latch input------------------------------------------------------------------------------------------------| Design Timing Summary| --------------------------------------------------------------------------------------------------------------------- WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -3.493 -65.048 20 711 0.069 0.000 0 711 2.400 0.000 0 363 Timing constraints are not met.------------------------------------------------------------------------------------------------| Clock Summary| -------------------------------------------------------------------------------------------------------------Clock Waveform(ns) Period(ns) Frequency(MHz)----- ------------ ---------- --------------TS_Q1_CLK1_GTREFCLK_PAD_P_IN {0.000 3.200} 6.400 156.250 TS_cntclk_p {0.000 10.000} 20.000 50.000 TS_sysclk_p {0.000 8.334} 16.668 59.995 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/RXOUTCLKFABRIC {0.000 3.200} 6.400 156.250 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK {0.000 3.200} 6.400 156.250 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLKFABRIC {0.000 3.200} 6.400 156.250 ------------------------------------------------------------------------------------------------| Intra Clock Table| -----------------------------------------------------------------------------------------------------------------Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- TS_Q1_CLK1_GTREFCLK_PAD_P_IN 5.228 0.000 0 7 0.172 0.000 0 7 2.420 0.000 0 12 TS_cntclk_p 17.389 0.000 0 20 0.249 0.000 0 20 9.600 0.000 0 21 TS_sysclk_p 13.674 0.000 0 548 0.108 0.000 0 548 7.934 0.000 0 264 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK 2.522 0.000 0 116 0.108 0.000 0 116 2.400 0.000 0 66 ------------------------------------------------------------------------------------------------| Inter Clock Table| -----------------------------------------------------------------------------------------------------------------From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- TS_cntclk_p gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK -3.493 -65.048 20 20 0.069 0.000 0 20 ------------------------------------------------------------------------------------------------| Other Path Groups Table| -----------------------------------------------------------------------------------------------------------------------Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------| Timing Details| -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------From Clock: TS_cntclk_p To Clock: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLKSetup : 20 Failing Endpoints, Worst Slack -3.493ns, Total Violation -65.048nsHold : 0 Failing Endpoints, Worst Slack 0.069ns, Total Violation 0.000ns---------------------------------------------------------------------------------------------------Max Delay Paths--------------------------------------------------------------------------------------Slack (VIOLATED) : -3.493ns (required time - arrival time) Source: cnt_out_reg[18]/C (rising edge-triggered cell FDRE clocked by TS_cntclk_p {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXCHARDISPVAL[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK Path Type: Setup (Max at Slow Process Corner) Requirement: 0.800ns (gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise@140.800ns - TS_cntclk_p rise@140.000ns) Data Path Delay: 1.266ns (logic 0.269ns (21.245%) route 0.997ns (78.755%)) Logic Levels: 0 Clock Path Skew: -1.856ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.430ns = ( 145.230 - 140.800 ) Source Clock Delay (SCD): 6.285ns = ( 146.285 - 140.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.664ns (DCD * PF) Destination Clock Delay (DCD): 4.430ns Prorating Factor (PF): 0.150 Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TS_cntclk_p rise edge) 140.000 140.000 r D15 0.000 140.000 r cntclk_p (IN) net (fo=0) 0.000 140.000 cntclk_p D15 IBUFDS (Prop_ibufds_I_O) 1.040 141.040 r cntclk_buf/O net (fo=1, routed) 1.904 142.944 cntclk BUFGCTRL_X0Y97 BUFG (Prop_bufg_I_O) 0.120 143.064 r cntclk_BUFG_inst/O net (fo=20, routed) 3.221 146.285 cntclk_BUFG SLR Crossing[3->1] SLICE_X515Y154 FDRE r cnt_out_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X515Y154 FDRE (Prop_fdre_C_Q) 0.269 146.554 r cnt_out_reg[18]/Q net (fo=2, routed) 0.997 147.552 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gt0_txdata_in[18] GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXCHARDISPVAL[1] ------------------------------------------------------------------- ------------------- (clock gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise edge) 140.800 140.800 r GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL 0.000 140.800 r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK net (fo=1, routed) 2.246 143.046 gtwizard_0_support_i/inst/gt_usrclk_source/GT0_TXOUTCLK_IN BUFGCTRL_X0Y32 BUFG (Prop_bufg_I_O) 0.113 143.159 r gtwizard_0_support_i/inst/gt_usrclk_source/txoutclk_bufg0_i/O net (fo=64, routed) 2.071 145.230 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/GT0_RXUSRCLK2_OUT GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 145.230 inter-SLR compensation -0.664 144.565 clock uncertainty -0.035 144.530 GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1]) -0.471 144.059 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i ------------------------------------------------------------------- required time 144.059 arrival time -147.552 ------------------------------------------------------------------- slack -3.493 Slack (VIOLATED) : -3.368ns (required time - arrival time) Source: cnt_out_reg[0]/C (rising edge-triggered cell FDRE clocked by TS_cntclk_p {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXDATA[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK Path Type: Setup (Max at Slow Process Corner) Requirement: 0.800ns (gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise@140.800ns - TS_cntclk_p rise@140.000ns) Data Path Delay: 1.143ns (logic 0.269ns (23.540%) route 0.874ns (76.460%)) Logic Levels: 0 Clock Path Skew: -1.855ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.430ns = ( 145.230 - 140.800 ) Source Clock Delay (SCD): 6.284ns = ( 146.284 - 140.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.664ns (DCD * PF) Destination Clock Delay (DCD): 4.430ns Prorating Factor (PF): 0.150 Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TS_cntclk_p rise edge) 140.000 140.000 r D15 0.000 140.000 r cntclk_p (IN) net (fo=0) 0.000 140.000 cntclk_p D15 IBUFDS (Prop_ibufds_I_O) 1.040 141.040 r cntclk_buf/O net (fo=1, routed) 1.904 142.944 cntclk BUFGCTRL_X0Y97 BUFG (Prop_bufg_I_O) 0.120 143.064 r cntclk_BUFG_inst/O net (fo=20, routed) 3.220 146.284 cntclk_BUFG SLR Crossing[3->1] SLICE_X517Y157 FDRE r cnt_out_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X517Y157 FDRE (Prop_fdre_C_Q) 0.269 146.553 r cnt_out_reg[0]/Q net (fo=2, routed) 0.874 147.427 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gt0_txdata_in[0] GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXDATA[0] ------------------------------------------------------------------- ------------------- (clock gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise edge) 140.800 140.800 r GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL 0.000 140.800 r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK net (fo=1, routed) 2.246 143.046 gtwizard_0_support_i/inst/gt_usrclk_source/GT0_TXOUTCLK_IN BUFGCTRL_X0Y32 BUFG (Prop_bufg_I_O) 0.113 143.159 r gtwizard_0_support_i/inst/gt_usrclk_source/txoutclk_bufg0_i/O net (fo=64, routed) 2.071 145.230 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/GT0_RXUSRCLK2_OUT GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 145.230 inter-SLR compensation -0.664 144.565 clock uncertainty -0.035 144.530 GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0]) -0.471 144.059 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i ------------------------------------------------------------------- required time 144.059 arrival time -147.427 ------------------------------------------------------------------- slack -3.368 Slack (VIOLATED) : -3.343ns (required time - arrival time) Source: cnt_out_reg[15]/C (rising edge-triggered cell FDRE clocked by TS_cntclk_p {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXDATA[13] (rising edge-triggered cell GTXE2_CHANNEL clocked by gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK {rise@0.000ns fall@3.200ns period=6.400ns}) Path Group: gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK Path Type: Setup (Max at Slow Process Corner) Requirement: 0.800ns (gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise@140.800ns - TS_cntclk_p rise@140.000ns) Data Path Delay: 1.117ns (logic 0.269ns (24.082%) route 0.848ns (75.918%)) Logic Levels: 0 Clock Path Skew: -1.856ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.430ns = ( 145.230 - 140.800 ) Source Clock Delay (SCD): 6.285ns = ( 146.285 - 140.000 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Inter-SLR Compensation: 0.664ns (DCD * PF) Destination Clock Delay (DCD): 4.430ns Prorating Factor (PF): 0.150 Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path. Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock TS_cntclk_p rise edge) 140.000 140.000 r D15 0.000 140.000 r cntclk_p (IN) net (fo=0) 0.000 140.000 cntclk_p D15 IBUFDS (Prop_ibufds_I_O) 1.040 141.040 r cntclk_buf/O net (fo=1, routed) 1.904 142.944 cntclk BUFGCTRL_X0Y97 BUFG (Prop_bufg_I_O) 0.120 143.064 r cntclk_BUFG_inst/O net (fo=20, routed) 3.221 146.285 cntclk_BUFG SLR Crossing[3->1] SLICE_X517Y154 FDRE r cnt_out_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X517Y154 FDRE (Prop_fdre_C_Q) 0.269 146.554 r cnt_out_reg[15]/Q net (fo=2, routed) 0.848 147.402 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gt0_txdata_in[15] GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXDATA[13] ------------------------------------------------------------------- ------------------- (clock gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK rise edge) 140.800 140.800 r GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL 0.000 140.800 r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXOUTCLK net (fo=1, routed) 2.246 143.046 gtwizard_0_support_i/inst/gt_usrclk_source/GT0_TXOUTCLK_IN BUFGCTRL_X0Y32 BUFG (Prop_bufg_I_O) 0.113 143.159 r gtwizard_0_support_i/inst/gt_usrclk_source/txoutclk_bufg0_i/O net (fo=64, routed) 2.071 145.230 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/GT0_RXUSRCLK2_OUT GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL r gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 145.230 inter-SLR compensation -0.664 144.565 clock uncertainty -0.035 144.530 GTXE2_CHANNEL_X0Y12 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13]) -0.471 144.059 gtwizard_0_support_i/inst/gtwizard_0_init_i/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i ------------------------------------------------------------------- required time 144.059 arrival time -147.402 ------------------------------------------------------------------- slack -3.343

嗨，如果你作为设计师认为必须分析这条路径（不要将其视为异步路径，因为从相位关系中看起来这看起来不像是相关时钟），那么使用Set_max_delay -datapath_only约束。
通常为了找到这个约束的值，我们需要1个时钟周期的快速时钟。谢谢，Yash



以下为原文

Hi,

If you as a designer thinks this path has to be analyzed (Not to be consider as async path because from the phase relation ship this looks like not related clocks) then use the Set_max_delay -datapath_only constraint. Usually to find the values of this constraint we take 1 clock cycle period of fast clock.

Thanks,
Yash

你好@ yashp
谢谢你的帮助！！！



以下为原文

Hello @yashp

Thanks for your help!!!