vivado zynq实现错误

您可以尝试在最新的Vivado工具中运行设计ISE或Vivado设计工具会根据电路拓扑自动选择合适的补偿。
但是在你的情况下，看起来它选择错误为ZHOLD。
当PLL的时钟输入来自BUFG时，补偿因子应为BUF_IN。
请参阅http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf的第85页。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

Can you try running the design in latest Vivado tool

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdfThanks and Regards
Balkrishan
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Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.View solution in original post

您可以尝试在最新的Vivado工具中运行设计ISE或Vivado设计工具会根据电路拓扑自动选择合适的补偿。
但是在你的情况下，看起来它选择错误为ZHOLD。
当PLL的时钟输入来自BUFG时，补偿因子应为BUF_IN。
请参阅http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf的第85页。
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Can you try running the design in latest Vivado tool

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdfThanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.