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我正在设计一款有助于Vivado的xc7v2000芯片。
我收到一个错误： 阶段1.3约束时钟/宏功率：[放置30-656]区域时钟缓冲器“PLLE2_U0”正在驱动761个BLOCKRAM负载，需要放置519个BLOCKRAM位置。 时钟缓冲器及其所有负载必须放在可路由的相同时钟区域中。 PLL位于CLOCK_REGION_X0Y3中，它只有49个BLOCKRAM位置，因此负载不能完全放置。分辨率：请分析您的设计以减少给定时钟的负载数量。 我尝试通过在PLL输出上添加BUFG来修复它但我得到了新问题： 第2阶段全球布局错误：[放置30-99] Placer因错误而失败：'无法放置BUFG'请在放置期间查看所有错误，严重警告和警告消息，以了解失败的原因.ERROR：[Common 17-69 ]命令失败：Placer无法放置所有实例 对于时钟输入，我使用专用的GCLK引脚，通过IBUFGDS缓冲器连接到PLL 我做错了什么？ 我怎么能诊断问题的根源？ 以上来自于谷歌翻译 以下为原文 I'm design a xc7v2000 chip with helps Vivado. I getting an error: Phase 1.3 Constrain Clocks/Macros ERROR: [Place 30-656] The regional clock buffer "PLLE2_U0" is driving 761 BLOCKRAM loads which require 519 BLOCKRAM locations to be placed. The clock buffer and all its loads must be placed in the same clock region to be routable. The PLL is placed in CLOCK_REGION_X0Y3 which only has 49 BLOCKRAM locations and thus the loads will not be fully placeable. Resolution: Please analyze your design to reduce the number of loads on the given clock. I try to fix it by adding BUFG on PLL output but I getting the new issue: Phase 2 Global Placement ERROR: [Place 30-99] Placer failed with error: 'Could not place BUFG' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. ERROR: [Common 17-69] Command failed: Placer could not place all instances For clock input I'm use dedicated GCLK pins which thru IBUFGDS buffer connects to PLL What I'm doing wrong? How to I'm could diagnose root of issue? 
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7个回答
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@ doka978，
您在哪个位置锁定BUFG？ 您的设计中有多少个BUFG？ 由于您使用的是SSI设备，请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf的第192页“SSI设备的附加时钟注意事项”。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 @doka978, At which location are you locking the BUFG? How many BUFG are present in your design? Since you are using SSI device, Refer to page-192 "Additional Clocking Considerations for SSI Devices" of http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------View solution in original post |
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@ doka978，
您在哪个位置锁定BUFG？ 您的设计中有多少个BUFG？ 由于您使用的是SSI设备，请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf的第192页“SSI设备的附加时钟注意事项”。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @doka978, At which location are you locking the BUFG? How many BUFG are present in your design? Since you are using SSI device, Refer to page-192 "Additional Clocking Considerations for SSI Devices" of http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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嗨，
根据第一条错误消息，您的理解是正确的，区域缓冲区不合适，需要转移到BUFG。 现在，当你搬到BUFG时，它是如何连接的？ 使用了多少％？ 请参阅http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf中的“SSI设备的附加时钟注意事项”第138页。 谢谢，佳日 以上来自于谷歌翻译 以下为原文 Hi, As per 1st error message your understanding is correct that regional buffer is not suitable and need to move to BUFG. Now as you moved to BUFG, how exactly it is being connected? How much % is utilized? Refer to "Additional Clocking considerations for SSI devices" page-138 of http://www.xilinx.com/support/documentation/sw_manuals/ug949-vivado-design-methodology.pdf Thanks, Yash |
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@syedz
>>你在哪个位置锁定BUFG？ 您的设计中有多少个BUFG？ 除引脚位置和时钟外没有任何限制 post_synth_util.rpt： 5.时钟----------- + ------------ + ------ + ------- + ----------- + ------- + | 网站类型| 二手| 固定| 可用| Util％| + ------------ + ------ + ------- + ----------- + ------ - + | BUFGCTRL | 53 | 0 | 128 | 41.4 || BUFIO | 0 | 0 | 96 | 0.00 || MMCME2_ADV | 0 | 0 | 24 | 0.00 || PLLE2_ADV | 1 | 0 | 24 | 4.17 || BUFMRCE | 0 | 0 | 48 | 0.00 || BUFHCE | 0 | 0 | 288 | 0.00 || BUFR | 0 | 0 | 96 | 0.00 | + ------------ + ------ + ------- + ----------- + ------- + 以上来自于谷歌翻译 以下为原文 @syedz >> At which location are you locking the BUFG? How many BUFG are present in your design? dont have any constraints except pin location and clocks post_synth_util.rpt: 5. Clocking ----------- +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ | BUFGCTRL | 53 | 0 | 128 | 41.4 | | BUFIO | 0 | 0 | 96 | 0.00 | | MMCME2_ADV | 0 | 0 | 24 | 0.00 | | PLLE2_ADV | 1 | 0 | 24 | 4.17 | | BUFMRCE | 0 | 0 | 48 | 0.00 | | BUFHCE | 0 | 0 | 288 | 0.00 | | BUFR | 0 | 0 | 96 | 0.00 | +------------+------+-------+-----------+-------+ |
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可能我选择了错误的GCLK引脚用于时钟输入？
我使用xc7v2000tfhg1761-2并将时钟源连接到pinAK34 [IO_L12P_T1_MRCC_14] 以上来自于谷歌翻译 以下为原文 Probably I choice wrong GCLK pin for clock input? I use xc7v2000tfhg1761-2 and connect clock source to pin AK34 [IO_L12P_T1_MRCC_14] |
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我通过手动重写RTL以解决某些代码中使用的BUFG来解决这个问题。
谢谢大家解释问题的根源 以上来自于谷歌翻译 以下为原文 I solved this issue by manually rewriting RTL to derceasing of BUFG used in some code. Thanks all for explanation the root of issue |
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我遇到了同样的问题。
你是如何重写rtl来减少使用的bufg的？ 我还有很多可以使用的bufg。 我应该在我的设计中实例化更多的bufg吗？ 感谢名单。 以上来自于谷歌翻译 以下为原文 i encountered the same issue. how did you rewrite rtl to reduce bufg used? i still have plenty of bufg that i can use. shall i instantiate more bufg in my design? thanx. |
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