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嗨,大家好,
在Zynq ultrascale +设备(xczu9eg-ffvb1156-2-e)上实现我的设计时,我注意到BRAM的急剧增加,导致实现失败。 合成后Vivado报道 2. BLOCKRAM ----------- + ------------------- + ------ + ------- + ----------- + - ----- + | 网站类型| 二手| 固定| 可用| Util%| + ------------------- + ------ + ------- + ----------- + - ----- + | Block RAM Tile | 902 | 0 | 912 | 98.90 | | RAMB36 / FIFO * | 0 | 0 | 912 | 0.00 | | RAMB18 | 1804 | 0 | 1824年| 98.90 | | 仅限RAMB18E2 | 1804 | | | | + ------------------- + ------ + ------- + ----------- + - ----- +虽然实现失败了 错误:[放置30-640]放置检查:此设计需要比目标设备中更多的RAMB18和RAMB36 / FIFO单元。 该设计需要2843个这样的小区类型,但目标设备中只有1824个兼容站点可用。 请分析您的综合结果和约束,以确保设计按预期映射到Xilinx原语。 如果是这样,请考虑定位更大的设备。 有关如何调查此增量背后原因的任何想法? 谢谢, 马克斯 以上来自于谷歌翻译 以下为原文 Hi everyone, while implementing my design on a Zynq ultrascale+ device (xczu9eg-ffvb1156-2-e) I've noticed a dramatic increase in the BRAM, which result in an implementation failure. After synthesis Vivado reported 2. BLOCKRAM-----------+-------------------+------+-------+-----------+-------+| Site Type | Used | Fixed | Available | Util% |+-------------------+------+-------+-----------+-------+| Block RAM Tile | 902 | 0 | 912 | 98.90 || RAMB36/FIFO* | 0 | 0 | 912 | 0.00 || RAMB18 | 1804 | 0 | 1824 | 98.90 || RAMB18E2 only | 1804 | | | |+-------------------+------+-------+-----------+-------+While the implementation fails with ERROR: [Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 2843 of such cell types but only 1824 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Any idea about how to investigate the reason behind this increment? Thanks, Max |
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4个回答
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合成期间有三个黑盒子(可能是IP模块)。
9.黑匣子 -------------- + ------------------------ + ------ + | 参考名称| 二手| + ------------------------ + ------ + | xilinx_mem_65536x64 | 4 | | xilinx_rom_4096x64 | 1 | | xilinx_clock_generator | 1 | + ------------------------ + ------ + 这些黑盒子是在合成过程中不可见的模块。 预先合成(称为上下文),生成自己的.dcp文件,然后在实现期间读入。 从他们的名字来看,至少有一个(可能是两个)是使用RAMB的块。 从它们的名称(和实例数),这些模块将使用另外520 RAMB36(或1040 RAMB18)。 这几乎(在一个内)恰好是实现过程所需的RAMB18数量 - 1804 + 1040 = 2844; 实现说它需要2843(一个RAM在某处得到优化)。 因此,您的设备被高度利用。 您需要找到一种方法来大幅减少RAM使用量。 如果你真的需要这么多RAM,你可能需要考虑使用外部RAM ...(或使用更大的设备) Avrum 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 You have three black boxes during synthesis (which are probably IP modules). 9. Black Boxes--------------+------------------------+------+| Ref Name | Used |+------------------------+------+| xilinx_mem_65536x64 | 4 || xilinx_rom_4096x64 | 1 || xilinx_clock_generator | 1 |+------------------------+------+ These black boxes are modules that are not visible during synthesis. The are pre-synthesized (called out-of-context), generating their own .dcp files, and are then read in during implementation. From their name, at least one (probably two) are blocks that use RAMB. From their names (and the number of instances), these modules will use an addition 520 RAMB36 (or 1040 RAMB18). This is almost (within one) exactly the number of RAMB18 that the implementation process says it needs - 1804+1040 = 2844; implementation says it needs 2843 (one RAM somewhere got optimized out). So your device is highly over-utilized. You will need to find a way to drastically reduce your RAM usage. If you really need this much RAM you may need to consider using external RAM... (or use a MUCH larger device) Avrum View solution in original post |
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嗨@ suppamax,
你能打开合成的原理图然后使用命令report_utilization然后检查BRAM的使用情况。 以上来自于谷歌翻译 以下为原文 Hi @suppamax, Can you please open the synthesized schematic and then use the command report_utilization then check the utilization of BRAM. |
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这是完整的报告
har_wrap_utilization_synth.txt 8 KB 以上来自于谷歌翻译 以下为原文 Here is the complete report har_wrap_utilization_synth.txt 8 KB |
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合成期间有三个黑盒子(可能是IP模块)。
9.黑匣子 -------------- + ------------------------ + ------ + | 参考名称| 二手| + ------------------------ + ------ + | xilinx_mem_65536x64 | 4 | | xilinx_rom_4096x64 | 1 | | xilinx_clock_generator | 1 | + ------------------------ + ------ + 这些黑盒子是在合成过程中不可见的模块。 预先合成(称为上下文),生成自己的.dcp文件,然后在实现期间读入。 从他们的名字来看,至少有一个(可能是两个)是使用RAMB的块。 从它们的名称(和实例数),这些模块将使用另外520 RAMB36(或1040 RAMB18)。 这几乎(在一个内)恰好是实现过程所需的RAMB18数量 - 1804 + 1040 = 2844; 实现说它需要2843(一个RAM在某处得到优化)。 因此,您的设备被高度利用。 您需要找到一种方法来大幅减少RAM使用量。 如果你真的需要这么多RAM,你可能需要考虑使用外部RAM ...(或使用更大的设备) Avrum 以上来自于谷歌翻译 以下为原文 You have three black boxes during synthesis (which are probably IP modules). 9. Black Boxes--------------+------------------------+------+| Ref Name | Used |+------------------------+------+| xilinx_mem_65536x64 | 4 || xilinx_rom_4096x64 | 1 || xilinx_clock_generator | 1 |+------------------------+------+ These black boxes are modules that are not visible during synthesis. The are pre-synthesized (called out-of-context), generating their own .dcp files, and are then read in during implementation. From their name, at least one (probably two) are blocks that use RAMB. From their names (and the number of instances), these modules will use an addition 520 RAMB36 (or 1040 RAMB18). This is almost (within one) exactly the number of RAMB18 that the implementation process says it needs - 1804+1040 = 2844; implementation says it needs 2843 (one RAM somewhere got optimized out). So your device is highly over-utilized. You will need to find a way to drastically reduce your RAM usage. If you really need this much RAM you may need to consider using external RAM... (or use a MUCH larger device) Avrum |
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