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我在设计放置阶段遇到此错误： “错误：[放置30-678]无法进行时钟区域分区：无法扩展net clk_gen / inst / clk_out1的时钟分区，以便具有足够的LUTRAM类型容量.Net有124720这种类型的负载，但总容量在 分区是112800Resolution：尝试去除在相同时钟区域中竞争资源的时钟（源和/或负载）上设置的区域约束。如果需要对时钟加载区域约束，请扩展区域 约束覆盖时钟源，或确保时钟源被约束/放置在与指定区域约束中的一个区域相同的行或列中的时钟区域中。同时尝试减少设计中的时钟资源量 ，通过组合一些时钟网或改变时钟基元的位置，以减少时钟路由利用率较高的区域中涉及的每个时钟网的源和负载之间的距离.ERROR：[Place 30-99] Placer使用erro失败 r：'全球布局后退出'请在放置期间查看所有错误，关键警告和警告信息，以了解失败的原因。“ 现在我不完全确定错误是什么。 它说一些关于LUTRAM的东西，比如分区的总容量是112800.我不确定这是否是由于使用太多的LUTRAM或这是一些时钟相关的错误。 资源利用率仅为55％，并且在可用的112800中仅使用了16128个基于LUT的DRAM。 请指导我这个错误的可能原因是什么？ 我曾在设计中使用过80％以上的资源，但从未遇到过这样的错误。 问候 以上来自于谷歌翻译 以下为原文 Hi All, I am getting this error while in design placement phase: "ERROR: [Place 30-678] Failed to do clock region partitioning: Could not expand clock partition for net clk_gen/inst/clk_out1 to have enough capacity for type LUTRAM. Net has 124720 loads of this type, but the total capacity in the partition is 112800 Resolution: Try removing the area constraints set on the clocks (source and/or loads) that compete for resources in the same clock region(s). In case an area constraint on the clock loads is necessary, please either extend the area constraint to cover the clock source, or make sure that the clock source is constrained/placed in a clock region in the same row or column as one of the regions in the specified area constraint. Also try reducing the amount of clock resources in your design, by either combining some clock nets or by changing the placement of clock primitives to reduce the distance between the source and loads of each clock net involved in the area with higher clock routing utilization. ERROR: [Place 30-99] Placer failed with error: 'Exit after global placer' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure." Now I am not completely sure what the error is about. It says something about LUTRAM like total capacity in the partition is 112800. I am not sure if this is caused by using too many LUTRAMs or this is some clock related error. Resource utilization is only 55% and only 16128 LUT based DRAMs are used out of the available 112800. Kindly guide me what is the possible cause of this error? I have worked in designs where more than 80% resources were used but never encountered such an error. Regards 
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6个回答
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@syedhabib，
这是时钟相关的错误。 你能检查错误信息中提到的网络的来源和负载吗？ 如错误消息中所述，如果它具有区域/局部约束，则工具无法将单元放置在相同的时钟区域中。 你能分享post opt dcp吗？ --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @syedhabib, This is clock related error. Can you check the source and loads of net mentioned in error message? As mentioned in error message, if it has area/loc constraints then tool is failing to place the cells in same clock region. Can you share the post opt dcp? --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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@syedz
先生，谢谢你的回复 我对时钟没有任何限制，只是它的周期应该是300 MHz。 我使用DCM生成250 MHz，用于整个设计。 我尝试将DCM输出时钟降低到100 MHz而不是250 MHz，我也尝试添加BUFG，我的两次尝试最终都出现了同样的错误。 我自己从未见过dcp文件。 我无法上传“test_wrapper_opt.dcp”文件。 那是你要我发送的文件吗？ 它的大小是19MB。 我已经发送了综合利用率报告和实施日志 问候 test_wrapper_utilization_synth.rpt 8 KB runme.log 13 KB 以上来自于谷歌翻译 以下为原文 @syedz Sir, Thanks for the reply I have no constraint on the clock except that its period should be 300 MHz. I use a DCM to generate 250 MHz that is used through out the design. I tried reducing the DCM output clock to 100 MHz instead of 250 MHz and I also tried adding BUFGs and both of my attempts ended up with same error. I have never seen the dcp file myself. I am unable to upload "test_wrapper_opt.dcp" file. is that the file you want me to send? it is 19MB in size. I have sent synthesis utilization report and implementation log Regards |
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@syedhabib，
是的，请分享test_wrapper_opt.dcp文件。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @syedhabib, Yes, please share the test_wrapper_opt.dcp file. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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分2部分发送
test_wrapper_opt.part1.rar 10240 KB 以上来自于谷歌翻译 以下为原文 Sending in 2 parts |
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test_wrapper_opt.part2.rar 9476 KB
以上来自于谷歌翻译 以下为原文 |
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@syedhabib，
我们已就此问题提交了CR并将其报告给了工厂。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @syedhabib, We have filed a CR for this issue and reported it to factory. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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