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嗨，
我正在使用Vivado 2018.1而且我在实现过去与早期版本的Vivado一起使用的IBUFDS_DIFF_OUT时遇到了麻烦。 我需要这个缓冲器用于差分输入，我需要正负信号。 错误消息： [Vivado 12-1411]无法设置端口的LOC属性，非法在站点HPIOBDIFFOUTBUF_X0Y79上放置实例xxx / IBUFDS / IBUFDS_0 / DIFFINBUF_INST。 位置站点类型（HPIOBDIFFOUTBUF）和bel类型（HPIOBDIFFOUTBUF_DIFFOUTBUF）与单元类型（DIFFINBUF）不匹配。 实例xxx / IBUFDS / IBUFDS_0 / DIFFINBUF_INST属于具有引用实例rx_1_n的形状。 形状元素相对于彼此具有相对位置。 无效位置可能是由形状中任何实例的约束引起的。 [“xxx / constraints_xxx.xdc”：28]约束： set_property PACKAGE_PIN V6 [get_ports rx_1_p]合成后，原理图显示了DIFFINBUF的两个实例。 一个输入连接到DIFF_IN_P，另一个输入连接到DIFF_IN_N。 如何摆脱此错误消息？ 以上来自于谷歌翻译 以下为原文 Hi, I'm using Vivado 2018.1 and I'm having troubles implementing a IBUFDS_DIFF_OUT that used to work with earlier versions of Vivado. I need this buffer for a differential input of which I need both the positive and the negative signal. The error message: [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance xxx/IBUFDS/IBUFDS_0/DIFFINBUF_INST on site HPIOBDIFFOUTBUF_X0Y79. The location site type (HPIOBDIFFOUTBUF) and bel type (HPIOBDIFFOUTBUF_DIFFOUTBUF) do not match the cell type (DIFFINBUF). Instance xxx/IBUFDS/IBUFDS_0/DIFFINBUF_INST belongs to a shape with reference instance rx_1_n. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["xxx/constraints_xxx.xdc":28]The constraint: set_property PACKAGE_PIN V6 [get_ports rx_1_p]After synthesis, the schematic shows two instances of DIFFINBUF. One with the p-input connected to DIFF_IN_P, the other with p-input connected to DIFF_IN_N. How can I get rid of this error message? 
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18个回答
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嗨马克，
TL; DR：当一个项目发生严重警告时，它将转移到同时打开的其他项目。 但警告不会存储到磁盘。 因此，重新启动Vivado将删除警告。 全文： 在关闭Vivado之后，当我打开任何检查点或整个项目时，我都没有收到严重警告。 显然，问题不会存储到文件中，但必须存在于vivados内存中。 这得到以下观察的支持： 当问题发生在一个项目中时，例如projectA，它也会发生在另一个同时打开的项目中，比如projectB。 只有在我打开精心设计，合成或实现的设计的原理图时才会出现警告。 但是一旦出现警告，即使在重新合成项目之后它也会停留或重新出现。 当警告从一个项目转移到另一个项目时，我怀疑存在问题我发现摆脱它的唯一方法是重置所有输出产品，包括生成的块设计。 也许仅仅关闭vivado并再次打开它就足够了。 每次运行都没有出现问题，很有可能你无法重现它。 如果我没记错的话，问题只发生在我同时打开多个项目时。 其中一个项目是Artix-7设备，另一个是Zynq US + 9EG ES2设备。 也许这导致了这个问题。 该警告通常首先出现在Zynq US +项目中。 由于我还没有使用Artix-7项目，我没有再出现这个问题。对我来说，问题解决了，因为我找到了一个解决方法（重启Vivado）。 由于似乎很难一致地重现问题，我建议我将问题标记为已解决。 最好的祝福， 托比亚斯 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi Marc, TL;DR: When the critical warning occurs in one project, it will sort of transfer to other projects open at the same time. But the warning does not get stored to disk. Therefore, restarting Vivado will remove the warning. Full Text: After closing Vivado, I don't get the critical warning when I open any checkpoint or the full project anymore. Apparently, the problem is not stored to the files but must be in vivados memory. This is supported by the following observation: When the problem had occurred in one project, say projectA, it would also occur in another project, say projectB, that was open at the same time. The warnings only appeared when I opened the schematics of the elaborated, synthesized or implemented designs. But once the warning had appeared, it would stay or reappear even after re-synthesis of the project. As the warning transfers from one project to another, I suspect there to be a problem The only way I found to get rid of it was to reset all output products, including the generated block designs. Maybe it would have been sufficient to just close vivado and open it again. The problem was not occurring in every run, and it is well possible that you wont be able to reproduce it. If I remember correctly, the problem only occurred when I had multiple projects open at the same time. One of these projects was for an Artix-7 device, the other for the Zynq US+ 9EG ES2 device. Maybe this has caused the problem. The warning usually first appeared in the Zynq US+ project. Since I haven't been working with an Artix-7 project anymore I did not have any more occurrences of the problem. For me, the problem is solved because I have found a workaround (restarting Vivado). As it appears to be difficult to consistently reproduce the problem, I would suggest that I mark the problem as solved. Best regards, Tobias View solution in original post |
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嗨马克，
TL; DR：当一个项目发生严重警告时，它将转移到同时打开的其他项目。 但警告不会存储到磁盘。 因此，重新启动Vivado将删除警告。 全文： 关闭Vivado后，当我打开任何检查点或整个项目时，我都没有收到严重警告。 显然，问题不会存储到文件中，但必须存在于vivados内存中。 这得到以下观察的支持： 当问题发生在一个项目中时，例如projectA，它也会发生在另一个同时打开的项目中，比如projectB。 只有在我打开精心设计，合成或实现的设计的原理图时才会出现警告。 但是一旦警告出现，即使重新合成项目，它也会停留或重新出现。 当警告从一个项目转移到另一个项目时，我怀疑存在问题我发现摆脱它的唯一方法是重置所有输出产品，包括生成的块设计。 也许仅仅关闭vivado并再次打开它就足够了。 问题并非在每次运行中都会发生，并且您很可能无法重现它。 如果我没记错的话，问题只发生在我同时打开多个项目时。 其中一个项目是Artix-7设备，另一个是Zynq US + 9EG ES2设备。 也许这导致了这个问题。 该警告通常首先出现在Zynq US +项目中。 由于我还没有使用Artix-7项目，我没有再出现这个问题。对我来说，问题解决了，因为我找到了一个解决方法（重启Vivado）。 由于似乎很难一致地重现问题，我建议我将问题标记为已解决。 最好的祝福， 托比亚斯 以上来自于谷歌翻译 以下为原文 Hi Marc, TL;DR: When the critical warning occurs in one project, it will sort of transfer to other projects open at the same time. But the warning does not get stored to disk. Therefore, restarting Vivado will remove the warning. Full Text: After closing Vivado, I don't get the critical warning when I open any checkpoint or the full project anymore. Apparently, the problem is not stored to the files but must be in vivados memory. This is supported by the following observation: When the problem had occurred in one project, say projectA, it would also occur in another project, say projectB, that was open at the same time. The warnings only appeared when I opened the schematics of the elaborated, synthesized or implemented designs. But once the warning had appeared, it would stay or reappear even after re-synthesis of the project. As the warning transfers from one project to another, I suspect there to be a problem The only way I found to get rid of it was to reset all output products, including the generated block designs. Maybe it would have been sufficient to just close vivado and open it again. The problem was not occurring in every run, and it is well possible that you wont be able to reproduce it. If I remember correctly, the problem only occurred when I had multiple projects open at the same time. One of these projects was for an Artix-7 device, the other for the Zynq US+ 9EG ES2 device. Maybe this has caused the problem. The warning usually first appeared in the Zynq US+ project. Since I haven't been working with an Artix-7 project anymore I did not have any more occurrences of the problem. For me, the problem is solved because I have found a workaround (restarting Vivado). As it appears to be difficult to consistently reproduce the problem, I would suggest that I mark the problem as solved. Best regards, Tobias |
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嗨，@ welo_zhaw，您设备的详细包装信息是什么？示例格式：xcku035-fbva900-2-e
-------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, @welo_zhaw , What's the detailed package information of your device? Example format: xcku035-fbva900-2-e------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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嗨@honghI我不知道，我不在办公室。
它是zcu102板，ES2.Regards，Tobias 以上来自于谷歌翻译 以下为原文 Hi @hongh I don‘t know by heart and I‘m out of office. It‘s the zcu102 board, ES2. Regards, Tobias |
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嗨，@ welo_zhaw，
我无法重现您遇到的问题。 IBUFDS_DIFF_OUT的端口是否用作时钟？ 请确认其他端口未使用U6。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, @welo_zhaw , I fail to reproduce the issue you met. Is the port for IBUFDS_DIFF_OUT used as clock? Please confirm that U6 is not used by the other port. ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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嗨@honghI使用端口进行差分输入，我在封装引脚视图中验证它们是否正确分组。端口用于差分数据输入。我将尝试在一个新项目中重现问题.Regards，Tobias
以上来自于谷歌翻译 以下为原文 Hi @hongh I use the port for a differential input, I verified in package pins view that they are correctly grouped. The port is used for differential data input. I will try in a new project to reproduce the problem. Regards, Tobias |
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嗨@welo_zhaw。
是否连接到输入和输出端口？ 该名称表示输入缓冲区，但该站点意味着输出缓冲区。 完整连接的示意图可能会有所帮助。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi @welo_zhaw. Is there connectivity to both an input and output port? The name implies an input buffer, but the site implies an output buffer. A schematic of the full connectivity might help. ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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你好@marcb
我想要使用的缓冲区是具有差分输出的差分输入缓冲区。 缓冲区的输出转到IDELAYE3原语，因此不应该是问题的根源。 这就是Elaborated Design的样子： 实施后： 好的，这很奇怪，因为问题不再发生了。 当它不工作时，IBUFDS_DIFF_OUT使用两个DIFFINBUF实现，一个是rx_2_p，rx_2_n连接到DIFF_IN_P和DIFF_IN_N，另一个连接是反转的。 只有每个DIFFINBUF的O端口被路由到IBUFCTRL。 这样，就需要四个IBUFCTRL，这可能导致放置失败。现在，实现似乎再次起作用，但我不清楚实际修复了什么问题。 我已经从锁定设备中删除了顶层模块，重置了输出产品，然后再次将模块添加到电路板设计中。 以上来自于谷歌翻译 以下为原文 Hi @marcb The buffer I want to use is a differential input buffer with differential output. The outputs of the buffer go to IDELAYE3 primitives, this should therefore not be a source of the problem. This is what the Elaborated Design looks like: And after Implementation: OK, this is strange, because the problem is not occurring anymore. When it wasn't working, the IBUFDS_DIFF_OUT was implemented using two DIFFINBUFs, one with rx_2_p and rx_2_n connected to DIFF_IN_P and DIFF_IN_N, and the other with the connections inverted. Only the O port of each DIFFINBUF was routed to a IBUFCTRL. This way, four IBUFCTRL would have been required, probably this was causing the placement failure. Now, the implementation seems to work again, but it is unclear to me what actually fixed the problem. I have removed the top modules from the lock desgin, reset the output products and then added the modules again to the board design. |
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嗨@marcb，
问题刚刚在另一轮实施后再次出现。 这是实现后的原理图。 我不知道造成这种情况的原因。 严重警告是： [Vivado 12-1411]无法设置端口的LOC属性，非法在站点HPIOBDIFFOUTBUF_X0Y69上放置实例xxx / US_PLUS_IDELAY.IBUFDS / IBUFDS_0 / DIFFINBUF_INST。 位置站点类型（HPIOBDIFFOUTBUF）和bel类型（HPIOBDIFFOUTBUF_DIFFOUTBUF）与单元类型（DIFFINBUF）不匹配。 实例xxx / US_PLUS_IDELAY.IBUFDS / IBUFDS_0 / DIFFINBUF_INST属于具有引用实例rx_2_n的形状。 形状元素相对于彼此具有相对位置。 无效位置可能是由形状中任何实例的约束引起的。 [“/xxx/srcs/io_serdes/constraints_zsync_zcu102.xdc":36] 以上来自于谷歌翻译 以下为原文 Hi @marcb, the problem just reappeared after another run of implementation. This is what the schematic looks like after Implementation. I have no idea what is causing this. The critical warning is: [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance xxx/US_PLUS_IDELAY.IBUFDS/IBUFDS_0/DIFFINBUF_INST on site HPIOBDIFFOUTBUF_X0Y69. The location site type (HPIOBDIFFOUTBUF) and bel type (HPIOBDIFFOUTBUF_DIFFOUTBUF) do not match the cell type (DIFFINBUF). Instance xxx/US_PLUS_IDELAY.IBUFDS/IBUFDS_0/DIFFINBUF_INST belongs to a shape with reference instance rx_2_n. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["/xxx/srcs/io_serdes/constraints_zsync_zcu102.xdc":36] |
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嗨，@ welo_zhaw，
你是说具有不同实施策略的相同综合结果，有时会出现问题，有时不会发生？ -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi, @welo_zhaw , Do you mean with same synthesized result with different implementation strategies, sometimes the issue occurs, sometimes doesn't occur? ------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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编辑：仅在打开已实施设计时发生严重警告。
以上来自于谷歌翻译 以下为原文 Edit: the critical warnings only occur when opening the Implemented Design. |
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你好@ welo_zhaw。
两个日志是否可用于比较？ 看来IBUFDS_DIFF_OUT宏的扩展方式不同。 希望这将显示结果不同的原因。 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi @welo_zhaw. Are the two logs available for comparison? It appears that the IBUFDS_DIFF_OUT macro is being expanded differently. Hopefully, this will show why the results are different. ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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你好@marcb
我不认为我必须再记录两次运行的文件。 如果您向我发送了您需要的日志说明，我将尝试获得一个好的和坏的例子。 检查点是否包含必要的信息？ 问候， 托比亚斯 以上来自于谷歌翻译 以下为原文 Hi @marcb I don't think I have to log files of both runs anymore. If you send me instructions which log you need I will try to get a good and bad example. Would a checkpoint contain the necessary info? Regards, Tobias |
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嗨@welo_zhaw，您可以在XX.runs / synth_1和XX.runs / impl_1中发布runme.log文件。在运行警告时，合成设计是否与实现的设计相同？
-------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi @welo_zhaw, You can post the runme.log file in both XX.runs/synth_1 and XX.runs/impl_1. In the run with warning, does the synthesized design look like same as the implemented one?------------------------------------------------------------------------- Don't forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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嗨@hongh
我可以确认，当错误发生时，合成和实现的设计看起来都是一样的。 我将从好的和坏的运行中将日志文件附加到此帖子。 而且我找到了引发警告的方法： 如果我在vivado中打开另一个项目时运行设计的综合/实现，则会发出警告。 这两个项目使用相同的源文件，但每个项目都有自己的项目目录。 一个项目（zcu102板）使用我的IP作为块设计中的模块。 bd存储在项目目录中，而不是存储在源目录中。 第二个项目（对于ac701板）有一个vhdl顶级文件来实例化我的IP。 警告可以在两个项目中的任何一个中发生。 问候， 托比亚斯 ibufds_error.zip 46 KB 以上来自于谷歌翻译 以下为原文 Hi @hongh I can confirm that when the error occurs, both the synthesized and the implemented designs look the same. I will attach log files to this post from a good and a bad run. And I have found a way to provoke the warning: If I run synthesis/implementation of the design while another project is open in vivado, the warning will be issued. These two projects use the same source files, but they have their own project directory each. One project (zcu102 board) uses my IP as a module in a block design. The bd is stored in the project directory, not in the source directory. The second project (for an ac701 board) has a vhdl top level file instantiating my IP. The warning can occur in either of the two projects. Regards, Tobias |
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你好@ welo_zhaw。
谢谢你的日志。 不幸的是，这并未发现任何更多信息。 除了下面的宏扩展匹配行，实现校验和也是如此。 这通常表示相同的结果。 IBUFDS_DIFF_OUT => IBUFDS_DIFF_OUT（DIFFINBUF，IBUFCTRL，IBUFCTRL）：1个实例 项目的失败版本是否可以发送？ -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Hi @welo_zhaw. Thanks for the logs. Unfortunately, this did not uncover any more information. Besides the below line of the macro expansion matching, so do the implementation checksums. This would normally indicate identical results. IBUFDS_DIFF_OUT => IBUFDS_DIFF_OUT (DIFFINBUF, IBUFCTRL, IBUFCTRL): 1 instances Is the failing version of the project available to send? ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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你好@marcb
是的，我可以发给你项目失败的版本。 我可以私下寄给你吗？ 此致，托比亚斯 以上来自于谷歌翻译 以下为原文 Hi @marcb yes, I can send you the failing version of the project. Can I send it to you in private? Regards, Tobias |
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嗨马克，
TL; DR：当一个项目发生严重警告时，它将转移到同时打开的其他项目。 但警告不会存储到磁盘。 因此，重新启动Vivado将删除警告。 全文： 在关闭Vivado之后，当我打开任何检查点或整个项目时，我都没有收到严重警告。 显然，问题不会存储到文件中，但必须存在于vivados内存中。 这得到以下观察的支持： 当问题发生在一个项目中时，例如projectA，它也会发生在另一个同时打开的项目中，比如projectB。 只有在我打开精心设计，合成或实现的设计的原理图时才会出现警告。 但是一旦出现警告，即使在重新合成项目之后它也会停留或重新出现。 当警告从一个项目转移到另一个项目时，我怀疑存在问题我发现摆脱它的唯一方法是重置所有输出产品，包括生成的块设计。 也许仅仅关闭vivado并再次打开它就足够了。 每次运行都没有出现问题，很有可能你无法重现它。 如果我没记错的话，问题只发生在我同时打开多个项目时。 其中一个项目是Artix-7设备，另一个是Zynq US + 9EG ES2设备。 也许这导致了这个问题。 该警告通常首先出现在Zynq US +项目中。 由于我还没有使用Artix-7项目，我没有再出现这个问题。对我来说，问题解决了，因为我找到了一个解决方法（重启Vivado）。 由于似乎很难一致地重现问题，我建议我将问题标记为已解决。 最好的祝福， 托比亚斯 以上来自于谷歌翻译 以下为原文 Hi Marc, TL;DR: When the critical warning occurs in one project, it will sort of transfer to other projects open at the same time. But the warning does not get stored to disk. Therefore, restarting Vivado will remove the warning. Full Text: After closing Vivado, I don't get the critical warning when I open any checkpoint or the full project anymore. Apparently, the problem is not stored to the files but must be in vivados memory. This is supported by the following observation: When the problem had occurred in one project, say projectA, it would also occur in another project, say projectB, that was open at the same time. The warnings only appeared when I opened the schematics of the elaborated, synthesized or implemented designs. But once the warning had appeared, it would stay or reappear even after re-synthesis of the project. As the warning transfers from one project to another, I suspect there to be a problem The only way I found to get rid of it was to reset all output products, including the generated block designs. Maybe it would have been sufficient to just close vivado and open it again. The problem was not occurring in every run, and it is well possible that you wont be able to reproduce it. If I remember correctly, the problem only occurred when I had multiple projects open at the same time. One of these projects was for an Artix-7 device, the other for the Zynq US+ 9EG ES2 device. Maybe this has caused the problem. The warning usually first appeared in the Zynq US+ project. Since I haven't been working with an Artix-7 project anymore I did not have any more occurrences of the problem. For me, the problem is solved because I have found a workaround (restarting Vivado). As it appears to be difficult to consistently reproduce the problem, I would suggest that I mark the problem as solved. Best regards, Tobias |
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如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
2461 浏览 15 评论
有输入，但是LVDS_25的FPGA内部接收不到数据，为什么？
1162浏览 1评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
584浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
451浏览 1评论
2005浏览 0评论
729浏览 0评论
/6 
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