生成比特流时收到错误

你好，
技术信息：董事会：ZCU104
Vivado 2018.1
附加日志文件
约束文件附加
确切的问题：
将以下两行添加到我的XDC文件中没有做任何事情来防止组合循环错误[DRC LUTLP-1]阻止比特流创建。
请提供更多方法来覆盖此错误。
set_property SEVERITY {警告} [get_drc_checks LUTLP-1]
set_property ALLOW_COMBINATORIAL_LOOPS是的
扩展说明：
我正在研究一个使用环形振荡器产生异步应力的研究项目，因此我无意去除组合环（环形振荡器）。
我尝试生成比特流时收到以下错误。
[DRC LUTLP-1]组合循环警报：10001 LUT细胞形成组合循环。
这可能会造成竞争条件。
时序分析可能不准确。
首选的解决方案是修改设计以移除组合逻辑循环。
如果循环已知并被理解，则可以通过确认条件并在循环中的任何一个网络上设置以下XDC约束来绕过此DRC：'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets]'。
循环中的一个网络是rings_inst / temp8 [0] _1。
请评估您的设计......（继续）我搜索了Xilinx 论坛，并按照下面链接的线程中的建议进行了搜索，
1. [Drc 23-20]规则违规（LUTLP-1）
2. [DRC 23-20]违反规则（LUTLP-1）（同一标题的第二个）
3.AR＃58828
4.调试组合循环
5.AR＃60591
6. [DRC 23-20]规则违规（LUTLP-1）组合循环
7. [Drc 23-20]规则违规（LUTLP-1）组合循环（同一标题的第二个）
这些都没有解决我的问题。
我想知道我可以采取哪些其他步骤来覆盖此错误。
我试过进去
set_property SEVERITY {警告} [get_drc_checks LUTLP-1]
set_property ALLOW_COMBINATORIAL_LOOPS TRUE直接进入Vivado TcL控制台，而不是XDC文件，但这没有任何效果。
错误消息本身表明我使用以下语法，
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets]
所以我尝试将以下行插入到我的XDC文件中，以便传递所有可能的环形振荡器实例。
set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ring_basys / rings_inst / temp *]
也许以上是正确的方法，但我的语法不正确？
ring_basys是我的顶级模块，rings_inst是包含环形振荡器的实体。
我再次重申，我不会删除这些组合循环，而只是试图找到一个可行的解决错误的方法。
谢谢，
标记
runme.log 171 KB
Constraints.txt 41 KB



以下为原文

Hello,

Technical Info:Board: ZCU104
Vivado 2018.1
log file attached
constraints file attached

Exact Problem:
Adding the follow two lines to my XDC file has done nothing to prevent the combinatorial loop error [DRC LUTLP-1] from preven ting bit stream creation. Please suggest more ways to override this error.


set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]set_property ALLOW_COMBINATORIAL_LOOPS TRUE
Expanded Explanation:
I am working on a research project that uses ring oscillators to create asynchronous stress so I have no intention of removing the combinatorial loops(ring oscillators). I receive the following error when I attempt to generate a bit-stream.


[DRC LUTLP-1] Combinatorial Loop Alert: 10001 LUT cells form a combinatorial loop.
This can create a race condition. Timing analysis may not be accurate. The preferred
resolution is to modify the design to remove combinatorial logic loops.
If the loop is known and understood, this DRC can be bypassed by acknowledging
the condition and setting the following XDC constraint on any one of the nets in the loop:
'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'.
One net in the loop is rings_inst/temp8[0]_1. Please evaluate your design... (Continues) I searched the Xilinx forums and followed the advice found in the threads linked below,

1. [Drc 23-20] Rule violation (LUTLP-1)
2. [DRC 23-20] Rule Violation (LUTLP-1) (second of same title)
3. AR# 58828
4. Debugging combinatorial loop
5. AR# 60591
6. [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop
7. [Drc 23-20] Rule violation (LUTLP-1) Combinatorial Loop (second of same title)

None of these has resolved my problem. I would like to know what other steps I can take to override this error. I have tried entering

set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]set_property ALLOW_COMBINATORIAL_LOOPS TRUEdirectly into the Vivado TcL console as opposed to in the XDC file but this had no effect.


The error message itself suggests that I use the following syntax,


set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]
So I tried inserting the following line into my XDC file in order to pass all possible ring oscillator instances.


set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ring_basys/rings_inst/temp*]
Maybe the above is the correct approach but my syntax is incorrect? ring_basys is my top module and rings_inst is the entity that contains the rings oscillators.

Once again I would like to repeat that I will not be removing these combinatorial loops and am simply trying to find a viable work around for the error.

Thank you,

Mark

runme.log ‏171 KB Constraints.txt ‏41 KB

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