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嗨，大家好。
当我完成实施时，会发生严重警告。如何解决这个问题？ 我正在尝试使用UltraScale + PCI Express集成块（1.3）。我将所有用户逻辑连接到PCI Express集成块，并连接了PCI Express外部端口。临界警告按摩是 “[Vivado 12-1411]无法设置端口的LOC属性，InstanceU_pcieip / ... pcie4_uscale_plus_0 ... / gthe4_channel_gen.gen_gthe4_channel_inst [3] .GTHE4_CHANNEL_PRIM_INST不能放在站点GTHE4_CHANNEL_X0Y12的GTHE4_CHANNEL中，因为bel被U_pcieip / ...占用 pcie4_uscale_plus_0 ... / gthe4_channel_gen.gen_gthe4_channel_inst [0] .GTHE4_CHANNEL_PRIM_INST（port :)。这可能是由于bel约束冲突引起的[“io.xdc”：439]“ 其他PCIe RX端口上也会出现相同的警告。 我的.xdc约束低于.set_property PACKAGE_PIN Y2 [get_ports RX0_P] set_property PACKAGE_PIN W4 [get_ports RX1_P] set_property PACKAGE_PIN V2 [get_ports RX2_P] set_property PACKAGE_PIN U4 [get_ports RX3_P] 器件引脚功能如下.Y2 MGTHRXP0W4 MGTHRXP1V2 MGTHRXP2U4 MGTHRXP3 我认为我的约束是正确的使用PCIe，但警告消息意味着这些端口被其他PCIe端口占用。然后，打开实现设计并看到I / O端口，引脚分配是变化的。 .xdc - >已实现designRX0（Y2） - > RX0（U4）RX1（W4） - > RX1（W4）RX2（V2） - > RX2（V2）RX3（U4） - > RX3（Y2） 工具版本：Vivado v2017.3 以上来自于谷歌翻译 以下为原文 Hi, everyone. When I finished implimentation, critical warning occures. How to solve this? I'm trying to use UltraScale+ PCI Express Integrated Block(1.3). I connected all user logic to PCI Express Integrated Block, and also connected PCI Express External ports. Critical warning massage is "[Vivado 12-1411] Cannot set LOC property of ports, Instance U_pcieip/...pcie4_uscale_plus_0.../gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y12 because the bel is occupied by U_pcieip/...pcie4_uscale_plus_0.../gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["io.xdc":439]" Same warning are occures on other PCIe RX ports. MY .xdc constraints below. set_property PACKAGE_PIN Y2 [get_ports RX0_P] set_property PACKAGE_PIN W4 [get_ports RX1_P] set_property PACKAGE_PIN V2 [get_ports RX2_P] set_property PACKAGE_PIN U4 [get_ports RX3_P] Device pin function is below. Y2 MGTHRXP0 W4 MGTHRXP1 V2 MGTHRXP2 U4 MGTHRXP3 I think my constraint are correct to use PCIe, But the warning message means these ports is occupied by other PCIe ports. And then, open implementation design and see I/O ports,pin assignment are change. .xdc -> Implemanted design RX0(Y2) -> RX0(U4) RX1(W4) -> RX1(W4) RX2(V2) -> RX2(V2) RX3(U4) -> RX3(Y2) Tool Version: Vivado v2017.3 
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这个问题可能是由于错误地使用IBUFDS_GTE2来进行MRCC。来自MRCC或SRCC的过分阻止，应该使用IBUFGDS / IBUFDS，而不是IBUFDS_GTE2。可以通过用IBUFGDS / IBUFDS替换IBUFDS_GTE2来解决问题。
如果您使用IPI流，也要检查此AR 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 This issue can occur due to incorrect use of IBUFDS_GTE2 for MRCCs. When differential clocks are coming from MRCCs or SRCCs, IBUFGDS/IBUFDS should be used, not an IBUFDS_GTE2. The problem can be resolved by replacing the IBUFDS_GTE2 with an IBUFGDS/IBUFDS. check this ARs as well if you using IPI flow Thanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution.View solution in original post |
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这个问题可能是由于错误地使用IBUFDS_GTE2来进行MRCC。来自MRCC或SRCC的过分阻止，应该使用IBUFGDS / IBUFDS，而不是IBUFDS_GTE2。可以通过用IBUFGDS / IBUFDS替换IBUFDS_GTE2来解决问题。
如果您使用IPI流，也要检查此AR 谢谢和RegardsBalkrishan ----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。 以上来自于谷歌翻译 以下为原文 This issue can occur due to incorrect use of IBUFDS_GTE2 for MRCCs. When differential clocks are coming from MRCCs or SRCCs, IBUFGDS/IBUFDS should be used, not an IBUFDS_GTE2. The problem can be resolved by replacing the IBUFDS_GTE2 with an IBUFGDS/IBUFDS. check this ARs as well if you using IPI flow Thanks and Regards Balkrishan -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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嗨Balkrishan。
感谢您的回复。 我使用IBUFDS而不是IBUFDS_GTH4，然后严重警告已经解决。 但我的项目是使用Ultrascale + FPGA，然后在IBUFDS_GTH4上实例化PCIe的参考时钟。 UG578 p.24https：//www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf 更改为IBUFDS后，PCIe参考时钟端口上将出现新的严重警告。 [Vivado 12-1411]无法设置端口的LOC属性，无法找到具有以下元素的形状的有效bel：CLK_PU_RefClk / IBUFCTRL_INSTCLK_NU_RefClk / DIFFINBUF_INST [“/ home / eita / project / VIVADO / const / io.xdc”： 438] 所以，我认为参考时钟必须使用IBUFDS_GTH4。 我会尝试更改参考时钟端口分配。 问候。 以上来自于谷歌翻译 以下为原文 Hi Balkrishan. Thanks for reply. I use IBUFDS instead of IBUFDS_GTH4, then critical warning has been resolved. But my project is using Ultrascale+ FPGA, then reference clock of PCIe is instantiated on IBUFDS_GTH4. UG578 p.24 https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf After change to IBUFDS, new Critical Warning become on PCIe reference clock port. [Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: CLK_P U_RefClk/IBUFCTRL_INST CLK_N U_RefClk/DIFFINBUF_INST ["/home/eita/project/VIVADO/const/io.xdc":438] So, I think reference clock must use IBUFDS_GTH4. I'll try to change reference clock port assigns. Regards. |
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嗨Balkrishan。
它已经解决了。 当我使用UltraScale + PCI Express集成块（1.3）时，IP块会生成xdc以进行引脚分配。 Vivado默认使用此xdc文件，因此用户xdc上的位置冲突occuers。 解决此问题的方法是，在xdc下面的用户位置约束之前设置一个空位置。 set_property PACKAGE_PIN {} [get_ports RX0_P] set_property PACKAGE_PIN {} [get_ports RX1_P] set_property PACKAGE_PIN {} [get_ports RX2_P] set_property PACKAGE_PIN {} [get_ports RX3_P] set_property PACKAGE_PIN Y2 [get_ports RX0_P] set_property PACKAGE_PIN W4 [get_ports RX1_P] set_property PACKAGE_PIN V2 [get_ports RX2_P] set_property PACKAGE_PIN U4 [get_ports RX3_P] 问候。 以上来自于谷歌翻译 以下为原文 Hi Balkrishan. It's solved. When I use UltraScale+ PCI Express Integrated Block(1.3), the IP Block generate xdc for pin assign. Vivado refer this xdc file by the default, so location conflict occuers on user xdc. Way to solve this issue, set an empty location before the user location constraint in xdc below. set_property PACKAGE_PIN {} [get_ports RX0_P]set_property PACKAGE_PIN {} [get_ports RX1_P]set_property PACKAGE_PIN {} [get_ports RX2_P]set_property PACKAGE_PIN {} [get_ports RX3_P]set_property PACKAGE_PIN Y2 [get_ports RX0_P]set_property PACKAGE_PIN W4 [get_ports RX1_P]set_property PACKAGE_PIN V2 [get_ports RX2_P]set_property PACKAGE_PIN U4 [get_ports RX3_P]Regards. |
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嗨，
我正面临着类似的问题并试用你的@ eita解决方案。 任何人都可以告诉我如何设置一个空位置才有帮助？ 怎么办？ 问候， 维奈 以上来自于谷歌翻译 以下为原文 Hi, I'm facing a similar issue and trying out your @eita solution. Can anyone tell me how does setting an empty location before will help? What is it going to do? Regards, Vinay |
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