1
完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
你好,
什么包含在UEF-ISE-SYSTEM-25许可证中? Vivado HLS是否适用于比Virtex-7更旧的设备? 这是浮动许可吗? 谢谢, 尤 以上来自于谷歌翻译 以下为原文 Hello, what exactly is included in the UEF-ISE-SYSTEM-25 license? Is there Vivado HLS for older devices than Virtex-7? Is this a floating license? Thanks, Viktor |
|
相关推荐
3个回答
|
|
你好Viktor,
UEF-ISE-SYSTEM-25许可证 - 这是ISE System_Edition许可证,不包括Vivado_HLS。 此类许可中包含以下功能:AccelDSP,ChipscopePro,ChipscopePro_SIOTK,ISE,ISIM,PlanAhead,SDK,SysGen,XPS。 大学许可证是浮动和节点锁定的。 只有大学才有这个选择。 有关详细信息,请联系您所在地区的Xilinx销售代表或FAE。 可在此处找到销售代表清单。 如果您已经或计划从Xilinx大学计划获得此类许可作为捐赠,如果您有任何其他问题,请直接发送电子邮件(xup@xilinx.com)。 有关Xilinx大学计划的详细信息,请访问此处 祝你今天愉快。 问候, 阿纳托利 亲切的问候,Anatoli Curran,Xilinx技术支持----------------------------------------- --------------------------------不要忘记回复,工作,并接受解决方案.---- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hello Viktor, UEF-ISE-SYSTEM-25 license – this is an ISE System_Edition license and it doesn’t include Vivado_HLS. The following features are included in such license: AccelDSP, ChipscopePro, ChipscopePro_SIOTK, ISE, ISIM, PlanAhead, SDK, SysGen, XPS. University licenses are both floating and node locked. Only universities get this option. For more info, please contact your Xilinx Sales Representative or FAE in your area. A list of Sales Representation can be found here. If you got or are planning to get such license from Xilinx University Program as a donation, please email them directly (xup@xilinx.com) if you have any additional questions. Details regarding the Xilinx University program can be found here Have a nice day. Regards, Anatoli Kind Regards, Anatoli Curran, Xilinx Technical Support ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
您好Anatoli,
来自Xilinx网站上的声明:“在保修期内,ISE Design Suite Logic Edition和Embedded Edition客户已经获得了Vivado Design Suite设计版和ISE Design Suite DSP和System Edition的新版Vivado Design Suite系统版本。 成本。” 据我所知,Vivado Design Suite系统版是ISE系统版(大学与否)的一部分。 但完整的Vivado仅支持7系列FPGA。 要支持旧部件,必须获得Sndndalone Vivado高级综合(Vivado_HLS功能)。 那是对的吗? 这个功能有大学定价吗? 问候, 尤 以上来自于谷歌翻译 以下为原文 Hello Anatoli, from the statement on the Xilinx web: "In warranty ISE Design Suite Logic Edition and Embedded Edition customers are already entitled to the Vivado Design Suite Design Edition and those with ISE Design Suite DSP and System Edition the new Vivado Design Suite System Edition at no additional cost." I understand that Vivado Design Suite System Edition is part of ISE System Edition (University or not). But full Vivado only supports 7 series FPGAs. To support older parts, one must obtain Standalone Vivado High-Level Synthesis (Vivado_HLS feature). Is that correct? Is there university pricing for this feature? Regards, Viktor |
|
|
|
嗨Viktor,
据我所知,此声明与保修期内购买的许可证有关,但与大学许可证无关。 因此,如果您对大学许可证(定价/捐赠问题或任何其他问题)有任何具体问题,请联系XUP(xup@xilinx.com)。 据我所知,如果您在Xilinx大学计划(XUP)下注册,您有权获得大学Vivado HLS许可的捐赠。 使用以下链接获取Xilinx和AutoESL / Vivado_HLS主页的详细信息:http://www.xilinx.com/university/tools/autoesl/index.htm。 问候, 阿纳托利 亲切的问候,Anatoli Curran,Xilinx技术支持----------------------------------------- --------------------------------不要忘记回复,工作,并接受解决方案.---- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hi Viktor, As I know this statement is related to the in-warranty purchased license, but not to the University licenses. As such, if you have any specific questions about university licenses (pricing/donation questions or any other questions), please contact XUP (xup@xilinx.com). As I know, if you are registered under Xilinx University Program (XUP), you are entitled to acquire a donation for Vivado HLS license for Universities. Use the below link for the home page of Xilinx and AutoESL/Vivado_HLS details http://www.xilinx.com/university/tools/autoesl/index.htm. Regards, Anatoli Kind Regards, Anatoli Curran, Xilinx Technical Support ------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2420 浏览 7 评论
2823 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2461 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1177浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
587浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
451浏览 1评论
2005浏览 0评论
731浏览 0评论
小黑屋| 手机版| Archiver| 德赢Vwin官网 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-23 22:36 , Processed in 1.440994 second(s), Total 82, Slave 66 queries .
Powered by 德赢Vwin官网 网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
德赢Vwin官网 观察
版权所有 © 湖南华秋数字科技有限公司
德赢Vwin官网 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号