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这是一个思维设计，而不是我正在积极努力的东西，但是： 我想分析一下比特流。比特流包含在时钟脉冲或两个时钟脉冲之间对齐的脉冲。没有明确的时钟信号，但我知道粗略的时钟速度，并且在比特流中嵌入同步序列。 （实际上是来自软盘驱动器的输入比特流。它是MFM编码的，具有大约500千赫的基础时钟。但细节并不重要。 解析比特流最合理的方法是在输入的比特流脉冲上触发，然后在1MHz时钟上采样。这样我就可以知道时钟信号是高还是低，关于它是什么样的脉冲。这似乎相当简单（尽管我确信细节中有魔鬼）。 然而。。。我的比特流将不完全是500千赫，因为它将由古老的和不可靠的机械硬件，即软盘驱动器产生。因此，我需要不知怎的同步我的时钟对传入的脉冲。考虑到PLL是围绕外部时钟同步设计的，我天真地期望只产生适当的时钟速率并将其连接到我的输入比特流，并且它将根据每一个脉冲自动重新同步。 PSOC5是现实的吗？ 查看时钟组件，我看不出任何方法来提供输入同步源。有一些提到同步，但没有什么看起来有用。有一个同步组件，但我不认为它是我想要的。我能用模拟组件构建PLL吗？我能配置SCB为我做这件事吗？基本上，我应该从哪里开始寻找？ 这似乎是合理的，这是可能的，毕竟，它基本上是一个UART… 以上来自于百度翻译 以下为原文 Hello, This is more a thought design than something I'm actively working on, but: I want to parse a bitstream. The bitstream contains pulses which are either aligned on a clock pulse or between two clock pulses. There is no explicit clock signal, but I know the rough clock speed and there are sync sequences embedded in the bitstream. (It's actually the incoming bitstream from a floppy disk drive. It's MFM encoded, with an underlying clock of about 500kHz. But the details aren't important.) It seems that the most sensible way to parse the bitstream is to trigger on the incoming bitstream pulse, and then sample on a 1MHz clock. That way I can tell from whether the clock signal is high or low about what kind of pulse it is. That seems relatively straightforward (although I'm sure the devil's in the details). However... my bitstream isn't going to be exactly 500kHz, because it's going to be generated by ancient and unreliable mechanical hardware, i.e. floppy disk drives. So I need to somehow sync my clock against the incoming pulses. Given that PLLs are designed around synchronising against external clocks, I would naively expect to just generate the appropriate rate of clock and connect it up to my input bitstream, and it would automatically resync based on every pulse. Is that realistic on a PSOC5? Looking at the Clock component, I don't see any way to provide an input sync source. There are some mentions of synchronisation but nothing that looks useful. There's a Sync component, but I don't think it does what I want. Can I build a PLL out of analogue components? Can I configure the SCB to do this for me out-of-the-box? Where, basically, should I start looking? It seems reasonable that this is possible; after all, it's basically a UART... 
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或者…（这不是我的主意，别人建议它）：
创建一个高速定时器，比如说8MHz。每当我收到一个输入的比特流脉冲，采样定时器，然后重置它。根据MFM转换类型，间隔将很好地分成1个、1.5个或2个刻度；然后直接给我的MFM解码状态机。 这避免了完全保留和同步比特流时钟的需要。它将基于输入的比特流自然地重新同步，并且在我放置桶边界的地方，边距完全在我的控制之下。它对PSoC5的优势也发挥了更大的作用。 以上来自于百度翻译 以下为原文 ...or (and this isn't my idea, someone else suggested it): Create a high-speed timer at, say, 8MHz. Whenever I receive a incoming bitstream pulse, sample the timer and then reset it. The intervals will nicely bucket into 1, 1.5 or 2 ticks depending on the MFM transition type; figuring out which is a couple of comparisons. That will then feed my MFM decode state machine directly. This avoids the need to maintain and synchronise the bitstream clock entirely. It'll naturally resynchronise based on the incoming bitstream and the margins are completely under my control based on where I put the bucket boundaries. It plays better to the Psoc5's strengths, too. |
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xixunled 发表于 2018-12-17 19:00 DavidGiven 只是游荡，你尝试标准UART读取传入数据吗？也许比特流足够稳定？ 奥迪赛1 以上来自于百度翻译 以下为原文 DavidGiven, Just wander, did you try standard UART to read incoming data? Maybe the bitstream is stable enough? odissey1 |
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我确实看过UART组件，但是你必须有一个启动位和至少一个停止位。我不认为（虽然还没有找到一个实际的确认），但是我的比特流有这些：它只是一个接一个的八位字节组。MFM编码，我想我实际上需要记录15位组在解码之前… 以上来自于百度翻译 以下为原文 I did look at the UART component, but AFAICT you have to have one start bit and at least one stop bit. I don't think (haven't found an actual confirmation yet, though) that my bitstream has these: it's just eight-bit byte groups one after another. And with the MFM encoding I think I would actually be needing to record 15-bit groups before doing the decoding... |
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