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一些多通道ADC设备具有SPI接口，其使用单个CLK信号，并且通过其自己的数据引脚同时发送每个信道的读取。我以前没有使用这个配置，我正在探索如何用PIC32 MZ连接到这样的设备。我的猜测是在主模式中使用一个SPI模块来提供CLK，3个其他从属模式，并将所有CLK信号连接在一起——见附加图像。我想知道这种方法在投入太多的时间和材料之前是否可行，有没有人成功地使用过这种安排？提议的方法在某些方面存在缺陷吗？打开建议。谢谢。
以上来自于百度翻译 以下为原文 Some multi-channel ADC devices have a SPI interface that uses a single CLK signal and transmits each channel's reading simultaneously over its own data pin. I have not worked with this arrangement before and I'm exploring how to connect to such a device with a PIC32MZ. My guess is to use one SPI module in master mode to provide CLK, 3 others in slave mode, and connect all CLK signals together -- see attached image. I'd like to know if this approach might work before investing too heavily in time and materials. Has anyone out there used this type of arrangement successfully? Is the proposed approach flawed in some way? Open to suggestions. Thanks. Attached Image(s) 
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15个回答
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从来没有使用过：但是我猜，使用PPS将SCK映射到4个不同的SPI模块（作为输入，一些PIC的要求也在作为主操作时）可以工作…
以上来自于百度翻译 以下为原文 Never used that: but I guess that using PPS to map SCK to 4 different SPI modules (as input, a requirement on some PICs also when operating as Master) could work... |
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尝试将SDI和SDO连接在一起。在读取时禁用SDO。添加串联电阻以避免总线争用。如果你的芯片支持它，你也可以使用开漏输出，但这可能会限制最高速度。总线收发器也是一种选择。最后选择一个更标准的芯片，这也是一个解决方案。
以上来自于百度翻译 以下为原文 Try connecting the SDI and SDO together. Disable the SDO when you are reading. Add a series resistor to avoid bus contention. If your chip supports it you could also use an open drain output, but that may limit the top speed. A bus transceiver would also be an option. And finally choosing a chip that is more standard whould also be a solution. |
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我不确定你是否能工作。你需要同时触发它们。一次触发一个会使它们失去同步。有一件事要看的是，许多SPI外设需要你设置时钟和英寸。如果你设置一个OUT和它们作为输入到该PIN，并触发它最后，这可能会起作用。你可能想看看钻头敲击是否足够快。
以上来自于百度翻译 以下为原文 I am not sure that you cuicuit will work. You would need to trigger them all at the same time. Triggering then one at a time would put them out of sync. One thing to look at is the many SPI peripherals need you to set clock out and in. If you set one as out and all of them as input to that pin, and trigger it last, that may work. You may want see if bit banging would be fast enough. |
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我可能没有在OP中指定我的问题的焦点。我可以使用SPI0作为SPI主控器来从其中一个通道读取，但是我需要配置SPI1-SPI3以接收来自其他3个通道的数据的建议，从而用一个CLK源读取所有4个通道。关于CLK信号的总线收发器。但我不确定SDI与SDO之间的联系会有什么帮助，你能详细说明一下吗？我已经跑过这个单一的CLK多DOT操作模式，同时测量多通道ADC部件。这听起来像是一种改进数据传输的好方法。
以上来自于百度翻译 以下为原文 I may not have specified the focal point of my question in the OP. I can use SPI0 as SPI master to read from one of the channels, but I wanted advice on configuring SPI1-SPI3 to receive data from the other 3 channels, thus reading all 4 channels with a single CLK source. @NKurzman : I see your point regarding bus transceiver for CLK signal. But I'm unsure how connecting SDI to SDO would help with this; can you elaborate on that? I have run across this single-CLK multi-DOUT mode of operation a number of times while surveying multi-channel ADC parts. It sounds like a neat way to improve data transfer. |
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我不熟悉的ADC SPI设备，你提到，但如果他们遵循标准的SPI接口规则，然后（1）连接CLK引脚从CPU到CLK引脚上的所有ADC CHIPS2）连接的MOSI（DO）引脚从CPU到MoSI（DI）引脚上的所有ADC CHIPS3）连接MISO（DI）管脚从CPU到所有ADC芯片4上的MISO（DO）引脚将每个I/O线从CPU连接到每个ADC芯片上的CS引脚。一个I/O对于每个芯片现在如果你想从一个ADC芯片读取，设置CS线低的芯片上，发送SPI命令，并获得阅读回来。SPI外设的工作方式是MISO引脚是三态，直到CS引脚低，所以您可以将所有MISO引脚连接在一起，只要每次只选择一个设备。
以上来自于百度翻译 以下为原文 I am not familiar with the ADC SPI device you mention, but if they follow the standard SPI interface rules, then 1) Connect the CLK pin from the CPU to the CLK pin on all the ADC chips 2) Connect the MOSI (DO) pin from the CPU to the MOSI (DI) pin on all the ADC chips 3) Connect the MISO (DI) pin from the CPU to the MISO (DO) pin on all the ADC chips 4) Connect individual I/O lines from the CPU to the CS pin on each ADC chip. one I/O for each chip Now if you want to get the reading from one ADC chip, set the CS line low on that chip, send the SPI command and get the reading back. The way SPI peripherals work is the MISO pins are tri-state until the CS pin is low, so you can connect all the MISO pins together, as long as only select one device at a time. |
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我想这不是OP的意思，但确实是正确的方法。
以上来自于百度翻译 以下为原文 I suppose this is not what OP meant |
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也许附在原始帖子上的图片并没有描述这一点，但是在这个场景中有1个ADC芯片——它有一个SPI时钟，和4个DUT引脚，可以被配置为同时传输。我试图看到如何配置PIC32 MZ接收所有这些数据。澄清：原来在附图中显示的ADC（AD77 64-4）需要在这种操作模式下成为总线主控器，所以在我的示例场景中，我没有使用好的部分。但是，ADC设备（例如TI ADS1274）看起来像我所描述的那样工作，其中ADC以SPI从属模式工作并且可以同时发送多个信道。我原来的问题仍然存在。
以上来自于百度翻译 以下为原文 Perhaps the picture attached to the original post did not depict this well, but there is 1 ADC chip in this scenario - it has a single SPI clock, and 4 DOUT pins that can be configured to transmit simultaneously. I was trying to see how I can configure the PIC32MZ to receive all this data at once. CLARIFICATION : It turns out that the ADC shown in the image attached to the original post (AD7768-4) needs to be bus master in that mode of operation, so I did not use a good part# in my sample scenario. But there are ADC devices (e.g. TI ADS1274) that appear to work as I depicted, where the ADC operates in SPI slave mode and can transmit multiple channels simultaneously. My original question still stands. |
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我认为你的电路很好（如果你想同时阅读）。我会添加一条CS线来同步奴隶，另一种方法是使用PMP。
以上来自于百度翻译 以下为原文 I think your circuit is fine (if you want to read simultaneously). I would add a CS line to synchronize slaves. Another way is to use PMP. |
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您的方法似乎是合理的，除了其他人已经注意到，确保所有四个模块开始接收相同的时钟周期。如果PIC32支持它，您可能需要使用“框架”模式中的所有四个SPI模块，由ADC的DRDYα输出触发。
以上来自于百度翻译 以下为原文 Your approach seems reasonable, except as others have noted, making sure all four modules start receiving on the same clock cycle. IF the PIC32 supports it, you may need to use all four SPI modules in "framed" mode, triggered by the DRDY# output from the ADC. |
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我感谢所有的反馈，也许是SQI？自从发布以来，我意识到PIC32 MZ外设“串行四接口”看起来像是设计与使用SPI总线多IO配置的外部设备一起工作。谢谢大家。如果我继续这样做，创建一个测试电路，我会报告什么工作，什么没有。
以上来自于百度翻译 以下为原文 I appreciate all the feedback. SQI, perhaps? Since posting I realized that the PIC32MZ peripheral "Serial Quad Interface" looks like it was designed to do work with external devices that use SPI bus multi-IO configurations. Thanks everyone. If I go forward with this and create a test circuit I'll report back on what worked and what didn't. |
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这看起来很奇怪。第一个SPI是主将一定能够接收ADC数据，但是不确定其他3个在从属模式中的SPI。它就像奴隶和奴隶一起用时钟信号提供外部。说，它可能工作，因为你是说，ADC将开始泵的数据在所有4针一旦收到时钟。所以尝试一下，它可以工作。也让我们知道结果。
以上来自于百度翻译 以下为原文 this looks little strange setup. first SPI which is MASTER will surely be able to receive ADC data but not sure about other 3 SPIs which are in slave mode. it is like slave talking to slave with clock signal provided externally. having said that, it might work as well because you are saying ADC will start pumping the data at all the 4 pins once it receives the clock. so just try it, it may work. let us know the outcome as well. |
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在后×1图像中的排列看起来不错，可以工作。
以上来自于百度翻译 以下为原文 The arrangement in Post #1 image looks okay and may work. |
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我认为SQI将以一种你不喜欢的方式来交织数据。
以上来自于百度翻译 以下为原文 I think SQI will interleave the data in a way you won't like. |
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DavidBLit：（你是对的。）在快速浏览（拓扑）上，它看起来像是一个可能的拟合，但是在手册中阅读它显示了你所说的：它是为一个非常特殊的协议设计的，它交错地跨越它的输出线。在最初的测试之后……以SPI1为主，SPI2为奴隶（其他）。2个尚未配置的SPI奴隶，并使用TI的ADS1274代替原来的图像中显示的ADC（它们具有相同的多DOUT接口，但TI是SPI从属），它看起来工作正常。我一到4点就试一下，如果发现问题，就汇报。对于任何感兴趣的（可能不是优化的，因为我对PIC32 MZ EF世界是新的）：* SPI1在SPI主机中被和谐地设置，* SPI2被和谐地设置为SPI从属，然后在AppMIXALILIZE（）中配置为SPI2CONCLRR＝0x00 000 8000；///SPI2模块关闭TunTestValay= SPI2BUF；//清除接收缓冲区IFS4CLR＝0x000 01C000；/ /清除任何现有事件。IEC4CLR＝0x000 01C000；//禁用RX、TX和错误中断。SPI2STATCLR＝0x40；//清除溢出SPI2CONSET＝0x00 000 8000；///SPI2模块* *然后在ISR响应/DRDY中，我有如下…在获取新数据之前，TestValay= SPI2BUF；//清除缓冲区。IFS4CLR＝0x000 01C000；/ /清除任何现有事件。SPI2STAT＝0x90000；//清除状态PLBIXSPIXBuffReWreE32位（SPIXIDID1，0x90000）；而（SPI2STAT＆AMP；0x000 000 0400＝＝0）{；}；LT；然后从SPI2BUF中检索值以用GT做…
以上来自于百度翻译 以下为原文 @DavidBLit : (RE SQI) you're right. At a quick glance (topologically) it looked like a possible fit, but reading up on it in the manual shows just what you said : it is designed for a very specific protocol that interleaves nibbles across its output lines. Follow-up after initial testing... With SPI1 as Master and SPI2 as slave (other 2 SPI slaves not configured yet), and using TI's ADS1274 instead of the ADC shown in the original images (they have same multi-DOUT interface but TI's is SPI slave), it seems to be working just fine. I'll try all 4 as soon as I get to it and report back if I find problems. For any interested (probably not optimized because I'm kind of new to the PIC32MZ EF world): * SPI1 is setup in Harmony as SPI master, * SPI2 is setup in Harmony as SPI slave, then configured in APP_Initialize() with SPI2CONCLR = 0x00008000; // // SPI2 module OFF TempTestVal = SPI2BUF; // Clears receive buffer IFS4CLR = 0x0001C000; // Clear any existing event. IEC4CLR = 0x0001C000; // Disable RX, TX, and Error interrupts. SPI2STATCLR = 0x40; // Clear overflow SPI2CONSET= 0x00008000; // // SPI2 module ON * then in the ISR responding to /DRDY, I have the following ... TestVal = SPI2BUF; // Clear buffer before getting new data. IFS4CLR = 0x0001C000; // Clear any existing event. SPI2STAT = 0x00000000; // Clear status PLIB_SPI_BufferWrite32bit(SPI_ID_1, 0x00000000); while (SPI2STAT & 0x00000400 == 0) { ; } ... |
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