CAN通信控制的位数据流处理器—Bit Stream Processor

2018-12-21 18:19:17 2936 CAN CAN通信数据流

0 位数据流处理器负责完成程序中所有有关数据的操作。位数据流处理器实际上就是一个序列发生器，它控制发送缓冲器、接收 FIFO 和 CAN 总线之间的数据流，同时它也执行错误检测、仲裁、位填充和 CAN 总线错误处理功能。位数据流处理器程序结构如图 9-11 所示。主要程序代码如下： //各个数据收发的起始状态 //接收数据的 idle 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_idle <= 1'b0; else if (reset_mode \| go_rx_id1 \| error_frame) rx_idle <=#Tp 1'b0; else if (go_rx_idle) rx_idle <=#Tp 1'b1; end // 接收数据的 id1 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_id1 <= 1'b0; else if (reset_mode \| go_rx_rtr1 \| error_frame) rx_id1 <=#Tp 1'b0; else if (go_rx_id1) rx_id1 <=#Tp 1'b1; end //接收数据的 rtr1 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_rtr1 <= 1'b0; else if (reset_mode \| go_rx_ide \| error_frame) rx_rtr1 <=#Tp 1'b0; else if (go_rx_rtr1) rx_rtr1 <=#Tp 1'b1; end //接收数据的 ide 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_ide <= 1'b0; else if (reset_mode \| go_rx_r0 \| go_rx_id2 \| error_frame) rx_ide <=#Tp 1'b0; else if (go_rx_ide) rx_ide <=#Tp 1'b1; end //接收数据的 id2 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_id2 <= 1'b0; else if (reset_mode \| go_rx_rtr2 \| error_frame) rx_id2 <=#Tp 1'b0; else if (go_rx_id2) rx_id2 <=#Tp 1'b1; end //接收数据的 rtr2 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_rtr2 <= 1'b0; else if (reset_mode \| go_rx_r1 \| error_frame) rx_rtr2 <=#Tp 1'b0; else if (go_rx_rtr2) rx_rtr2 <=#Tp 1'b1; end //接收数据的 r0 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_r1 <= 1'b0; else if (reset_mode \| go_rx_r0 \| error_frame) rx_r1 <=#Tp 1'b0; else if (go_rx_r1) rx_r1 <=#Tp 1'b1; end //接收数据的 r0 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_r0 <= 1'b0; else if (reset_mode \| go_rx_dlc \| error_frame) rx_r0 <=#Tp 1'b0; else if (go_rx_r0) rx_r0 <=#Tp 1'b1; end //接收数据的 dlc 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_dlc <= 1'b0; else if (reset_mode \| go_rx_data \| go_rx_crc \| error_frame) rx_dlc <=#Tp 1'b0; else if (go_rx_dlc) rx_dlc <=#Tp 1'b1; end //接收数据状态 always @ (posedge clk or posedge rst) begin if (rst) rx_data <= 1'b0; else if (reset_mode \| go_rx_crc \| error_frame) rx_data <=#Tp 1'b0; else if (go_rx_data) rx_data <=#Tp 1'b1; end // 接收数据的 crc 状态 always @ (posedge clk or posedge rst) begin if (rst) rx_crc <= 1'b0; else if (reset_mode \| go_rx_crc_lim \| error_frame) rx_crc <=#Tp 1'b0; else if (go_rx_crc) rx_crc <=#Tp 1'b1; end //接收数据 crc 分隔符状态 always @ (posedge clk or posedge rst) begin if (rst) rx_crc_lim <= 1'b0; else if (reset_mode \| go_rx_ack \| error_frame) rx_crc_lim <=#Tp 1'b0; else if (go_rx_crc_lim) rx_crc_lim <=#Tp 1'b1; end //接收数据的应答状态 always @ (posedge clk or posedge rst) begin if (rst) rx_ack <= 1'b0; else if (reset_mode \| go_rx_ack_lim \| error_frame) rx_ack <=#Tp 1'b0; else if (go_rx_ack) rx_ack <=#Tp 1'b1; end //接收数据分隔符状态 always @ (posedge clk or posedge rst) begin if (rst) rx_ack_lim <= 1'b0; else if (reset_mode \| go_rx_eof \| error_frame) rx_ack_lim <=#Tp 1'b0; else if (go_rx_ack_lim) rx_ack_lim <=#Tp 1'b1; end //接收数据的帧尾状态 always @ (posedge clk or posedge rst) begin if (rst) rx_eof <= 1'b0; else if (go_rx_inter \| error_frame \| go_overload_frame) rx_eof <=#Tp 1'b0; else if (go_rx_eof) rx_eof <=#Tp 1'b1; end //帧间空间状态 always @ (posedge clk or posedge rst) begin if (rst) rx_inter <= 1'b0; else if (reset_mode \| go_rx_idle \| go_rx_id1 \| go_overload_frame \| go_error_frame) rx_inter <=#Tp 1'b0; else if (go_rx_inter) rx_inter <=#Tp 1'b1; end // ID 寄存器 always @ (posedge clk or posedge rst) begin if (rst) id <= 0; else if (sample_point & (rx_id1 \| rx_id2) & (~bit_de_stuff)) id <=#Tp {id[27:0], sampled_bit}; end // rtr1 位 always @ (posedge clk or posedge rst) begin if (rst) rtr1 <= 0; else if (sample_point & rx_rtr1 & (~bit_de_stuff)) rtr1 <=#Tp sampled_bit; end // rtr2 位 always @ (posedge clk or posedge rst) begin if (rst) rtr2 <= 0; else if (sample_point & rx_rtr2 & (~bit_de_stuff)) rtr2 <=#Tp sampled_bit; end // ide 位 always @ (posedge clk or posedge rst) begin if (rst) ide <= 0; else if (sample_point & rx_ide & (~bit_de_stuff)) ide <=#Tp sampled_bit; end // 获得数据长度 always @ (posedge clk or posedge rst) begin if (rst) data_len <= 0; else if (sample_point & rx_dlc & (~bit_de_stuff)) data_len <=#Tp {data_len[2:0], sampled_bit}; end // 获得数据 always @ (posedge clk or posedge rst) begin if (rst) tmp_data <= 0; else if (sample_point & rx_data & (~bit_de_stuff)) tmp_data <=#Tp {tmp_data[6:0], sampled_bit}; end always @ (posedge clk or posedge rst) begin if (rst) write_data_to_tmp_fifo <= 0; else if (sample_point & rx_data & (~bit_de_stuff) & (&bit_cnt[2:0])) write_data_to_tmp_fifo <=#Tp 1'b1; else write_data_to_tmp_fifo <=#Tp 0; end always @ (posedge clk or posedge rst) begin if (rst) byte_cnt <= 0; else if (write_data_to_tmp_fifo) byte_cnt <=#Tp byte_cnt + 1; else if (reset_mode \| (sample_point & go_rx_crc_lim)) byte_cnt <=#Tp 0; end always @ (posedge clk) begin if (write_data_to_tmp_fifo) tmp_fifo[byte_cnt] <=#Tp tmp_data; end // CRC 校验数据 always @ (posedge clk or posedge rst) begin if (rst) crc_in <= 0; else if (sample_point & rx_crc & (~bit_de_stuff)) crc_in <=#Tp {crc_in[13:0], sampled_bit}; end //计数器 always @ (posedge clk or posedge rst) begin if (rst) bit_cnt <= 0; else if (go_rx_id1 \| go_rx_id2 \| go_rx_dlc \| go_rx_data \| go_rx_crc \| go_rx_ack \| go_rx_eof \| go_rx_inter \| go_error_frame \| go_overload_frame) bit_cnt <=#Tp 0; else if (sample_point & (~bit_de_stuff)) bit_cnt <=#Tp bit_cnt + 1'b1; end //帧尾计数器 always @ (posedge clk or posedge rst) begin if (rst) eof_cnt <= 0; else if (sample_point) begin if (reset_mode \| go_rx_inter \| go_error_frame \| go_overload_frame) eof_cnt <=#Tp 0; else if (rx_eof) eof_cnt <=#Tp eof_cnt + 1'b1; end end // 使能位填充 always @ (posedge clk or posedge rst) begin if (rst) bit_stuff_cnt_en <= 1'b0; else if (bit_de_stuff_set) bit_stuff_cnt_en <=#Tp 1'b1; else if (bit_de_stuff_reset) bit_stuff_cnt_en <=#Tp 1'b0; end //位填充计数器 always @ (posedge clk or posedge rst) begin if (rst) bit_stuff_cnt <= 1; else if (bit_de_stuff_reset) bit_stuff_cnt <=#Tp 1; else if (sample_point & bit_stuff_cnt_en) begin if (bit_stuff_cnt == 5) bit_stuff_cnt <=#Tp 1; else if (sampled_bit == sampled_bit_q) bit_stuff_cnt <=#Tp bit_stuff_cnt + 1'b1; else bit_stuff_cnt <=#Tp 1; end end // 发送数据的使能位填充 always @ (posedge clk or posedge rst) begin if (rst) bit_stuff_cnt_tx_en <= 1'b0; else if (bit_de_stuff_set & transmitting) bit_stuff_cnt_tx_en <=#Tp 1'b1; else if (bit_de_stuff_reset) bit_stuff_cnt_tx_en <=#Tp 1'b0; end //发送数据的位填充计数 always @ (posedge clk or posedge rst) begin if (rst) bit_stuff_cnt_tx <= 1; else if (bit_de_stuff_reset) bit_stuff_cnt_tx <=#Tp 1; else if (tx_point_q & bit_stuff_cnt_en) begin if (bit_stuff_cnt_tx == 5) bit_stuff_cnt_tx <=#Tp 1; else if (tx == tx_q) bit_stuff_cnt_tx <=#Tp bit_stuff_cnt_tx + 1'b1; else bit_stuff_cnt_tx <=#Tp 1; end end assign bit_de_stuff = bit_stuff_cnt == 5; assign bit_de_stuff_tx = bit_stuff_cnt_tx == 5; //位填充错误 assign stuff_err = sample_point & bit_stuff_cnt_en & bit_de_stuff & (sampled_bit == sampled_bit_q); //产生延迟信号 always @ (posedge clk) begin reset_mode_q <=#Tp reset_mode; node_bus_off_q <=#Tp node_bus_off; end always @ (posedge clk or posedge rst) begin if (rst) crc_enable <= 1'b0; else if (go_crc_enable) crc_enable <=#Tp 1'b1; else if (reset_mode \| rst_crc_enable) crc_enable <=#Tp 1'b0; end //CRC 校验错误 always @ (posedge clk or posedge rst) begin if (rst) crc_err <= 1'b0; else if (go_rx_ack) crc_err <=#Tp crc_in != calculated_crc; else if (reset_mode \| error_frame_ended) crc_err <=#Tp 1'b0; end // 一般错误的条件 assign form_err = sample_point & ( ((~bit_de_stuff) & rx_ide & sampled_bit & (~rtr1)) \| (rx_crc_lim & (~sampled_bit)) \| (rx_ack_lim & (~sampled_bit)) \| ((eof_cnt < 6) & rx_eof & (~sampled_bit) & (~tx_state) ) \| (& rx_eof & (~sampled_bit) & tx_state)); always @ (posedge clk or posedge rst) begin if (rst) ack_err_latched <= 1'b0; else if (reset_mode \| error_frame_ended \| go_overload_frame) ack_err_latched <=#Tp 1'b0; else if (ack_err) ack_err_latched <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) bit_err_latched <= 1'b0; else if (reset_mode \| error_frame_ended \| go_overload_frame) bit_err_latched <=#Tp 1'b0; else if (bit_err) bit_err_latched <=#Tp 1'b1; end //规则 5 assign rule5 = (~node_error_passive) & bit_err & (error_frame & (error_cnt1 < 7) \| overload_frame & (overload_cnt1 < 7) ); //规则 3 always @ (posedge clk or posedge rst) begin if (rst) rule3_exc1_1 <= 1'b0; else if (reset_mode \| error_flag_over \| rule3_exc1_2) rule3_exc1_1 <=#Tp 1'b0; else if (transmitter & node_error_passive & ack_err) rule3_exc1_1 <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) rule3_exc1_2 <= 1'b0; else if (reset_mode \| error_flag_over) rule3_exc1_2 <=#Tp 1'b0; else if (rule3_exc1_1) rule3_exc1_2 <=#Tp 1'b1; else if ((error_cnt1 < 7) & sample_point & (~sampled_bit)) rule3_exc1_2 <=#Tp 1'b0; end always @ (posedge clk or posedge rst) begin if (rst) rule3_exc2 <= 1'b0; else if (reset_mode \| error_flag_over) rule3_exc2 <=#Tp 1'b0; else if (transmitter & stuff_err & arbitration_field & sample_point & tx & (~sampled_bit)) rule3_exc2 <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) stuff_err_latched <= 1'b0; else if (reset_mode \| error_frame_ended \| go_overload_frame) stuff_err_latched <=#Tp 1'b0; else if (stuff_err) stuff_err_latched <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) form_err_latched <= 1'b0; else if (reset_mode \| error_frame_ended \| go_overload_frame) form_err_latched <=#Tp 1'b0; else if (form_err) form_err_latched <=#Tp 1'b1; end //接收数据的 CRC 校验 can_crc i_can_crc_rx ( .clk(clk), .data(sampled_bit), .enable(crc_enable & sample_point & (~bit_de_stuff)), .initialize(go_crc_enable), .crc(calculated_crc) ); assign no_byte0 = rtr1 \| (data_len<1); assign no_byte1 = rtr1 \| (data_len<2); // 接收数据 FIFO 的写使能 always @ (posedge clk or posedge rst) begin if (rst) wr_fifo <= 1'b0; else if (reset_wr_fifo) wr_fifo <=#Tp 1'b0; else if (go_rx_inter & id_ok & (~error_frame_ended) & ((~tx_state) \| self_rx_request)) wr_fifo <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) header_cnt <= 0; else if (reset_wr_fifo) header_cnt <=#Tp 0; else if (wr_fifo & storing_header) header_cnt <=#Tp header_cnt + 1; end //数据计数器 always @ (posedge clk or posedge rst) begin if (rst) data_cnt <= 0; else if (reset_wr_fifo) data_cnt <=#Tp 0; else if (wr_fifo) data_cnt <=#Tp data_cnt + 1; end // 数据的合成并保存到 FIFO 中 always @ (extended_mode or ide or data_cnt or header_cnt or header_len or storing_header or id or rtr1 or rtr2 or data_len or tmp_fifo[0] or tmp_fifo[2] or tmp_fifo[4] or tmp_fifo[6] or tmp_fifo[1] or tmp_fifo[3] or tmp_fifo[5] or tmp_fifo[7]) begin if (storing_header) begin if (extended_mode) // extended mode begin if (ide) // extended format begin case (header_cnt) // synthesis parallel_case 3'h0 : data_for_fifo <= {1'b1, rtr2, 2'h0, data_len}; 3'h1 : data_for_fifo <= id[28:21]; 3'h2 : data_for_fifo <= id[20:13]; 3'h3 : data_for_fifo <= id[12:5]; 3'h4 : data_for_fifo <= {id[4:0], 3'h0}; default: data_for_fifo <= 0; endcase end else // standard format begin case (header_cnt) // synthesis parallel_case 3'h0 : data_for_fifo <= {1'b0, rtr1, 2'h0, data_len}; 3'h1 : data_for_fifo <= id[10:3]; 3'h2 : data_for_fifo <= {id[2:0], 5'h0}; default: data_for_fifo <= 0; endcase end end else // normal mode begin case (header_cnt) // synthesis parallel_case 3'h0 : data_for_fifo <= id[10:3]; 3'h1 : data_for_fifo <= {id[2:0], rtr1, data_len}; default: data_for_fifo <= 0; endcase end end else data_for_fifo <= tmp_fifo[data_cnt-header_len]; end // 传输错误帧 always @ (posedge clk or posedge rst) begin if (rst) error_frame <= 1'b0; else if (reset_mode \| error_frame_ended \| go_overload_frame) error_frame <=#Tp 1'b0; else if (go_error_frame) error_frame <=#Tp 1'b1; end always @ (posedge clk) begin if (sample_point) error_frame_q <=#Tp error_frame; end always @ (posedge clk or posedge rst) begin if (rst) error_cnt1 <= 1'b0; else if (reset_mode \| error_frame_ended \| go_error_frame \| go_overload_frame) error_cnt1 <=#Tp 1'b0; else if (error_frame & tx_point & (error_cnt1 < 7)) error_cnt1 <=#Tp error_cnt1 + 1'b1; end assign error_flag_over = ((~node_error_passive) & sample_point & (error_cnt1 == 7) \| node_error_passive & sample_point & (passive_cnt == 5)) & (~enable_error_cnt2); always @ (posedge clk or posedge rst) begin if (rst) error_flag_over_blocked <= 1'b0; else if (reset_mode \| error_frame_ended \| go_error_frame \| go_overload_frame) error_flag_over_blocked <=#Tp 1'b0; else if (error_flag_over) error_flag_over_blocked <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) enable_error_cnt2 <= 1'b0; else if (reset_mode \| error_frame_ended \| go_error_frame \| go_overload_frame) enable_error_cnt2 <=#Tp 1'b0; else if (error_frame & (error_flag_over & sampled_bit)) enable_error_cnt2 <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) error_cnt2 <= 0; else if (reset_mode \| error_frame_ended \| go_error_frame \| go_overload_frame) error_cnt2 <=#Tp 0; else if (enable_error_cnt2 & tx_point) error_cnt2 <=#Tp error_cnt2 + 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) delayed_dominant_cnt <= 0; else if (reset_mode \| enable_error_cnt2 \| go_error_frame \| enable_overload_cnt2 \| go_overload_frame) delayed_dominant_cnt <=#Tp 0; else if (sample_point & (~sampled_bit) & ((error_cnt1 == 7) \| (overload_cnt1 == 7))) delayed_dominant_cnt <=#Tp delayed_dominant_cnt + 1'b1; end //被动计数 always @ (posedge clk or posedge rst) begin if (rst) passive_cnt <= 0; else if (reset_mode \| error_frame_ended \| go_error_frame \| go_overload_frame) passive_cnt <=#Tp 0; else if (sample_point & (passive_cnt < 5)) begin if (error_frame_q & (~enable_error_cnt2) & (sampled_bit == sampled_bit_q)) passive_cnt <=#Tp passive_cnt + 1'b1; else passive_cnt <=#Tp 0; end end // 传输超载帧 always @ (posedge clk or posedge rst) begin if (rst) overload_frame <= 1'b0; else if (reset_mode \| overload_frame_ended \| go_error_frame) overload_frame <=#Tp 1'b0; else if (go_overload_frame) overload_frame <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) overload_cnt1 <= 1'b0; else if (reset_mode \| overload_frame_ended \| go_error_frame \| go_overload_frame) overload_cnt1 <=#Tp 1'b0; else if (overload_frame & tx_point & (overload_cnt1 < 7)) overload_cnt1 <=#Tp overload_cnt1 + 1'b1; end assign overload_flag_over = sample_point & (overload_cnt1 == 7) & (~enable_overload_cnt2); always @ (posedge clk or posedge rst) begin if (rst) enable_overload_cnt2 <= 1'b0; else if (reset_mode \| overload_frame_ended \| go_error_frame \| go_overload_frame) enable_overload_cnt2 <=#Tp 1'b0; else if (overload_frame & (overload_flag_over & sampled_bit)) enable_overload_cnt2 <=#Tp 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) overload_cnt2 <= 0; else if (reset_mode \| overload_frame_ended \| go_error_frame \| go_overload_frame) overload_cnt2 <=#Tp 0; else if (enable_overload_cnt2 & tx_point) overload_cnt2 <=#Tp overload_cnt2 + 1'b1; end always @ (posedge clk or posedge rst) begin if (rst) overload_frame_blocked <= 0; else if (reset_mode \| go_error_frame \| go_rx_id1) overload_frame_blocked <=#Tp 0; else if (go_overload_frame & overload_frame) // This is a second sequential overload overload_frame_blocked <=#Tp 1'b1; end assign send_ack = (~tx_state) & rx_ack & (~err) & (~listen_only_mode); always @ (posedge clk or posedge rst) begin if (rst) tx <= 1'b1; else if (reset_mode) // Reset tx <=#Tp 1'b1; else if (tx_point) begin if (tx_state) // 传输报文 tx <=#Tp ((~bit_de_stuff_tx) & tx_bit) \| (bit_de_stuff_tx & (~tx_q)); else if (send_ack) // 应答 tx <=#Tp 1'b0; else if (overload_frame) //传输超载帧 begin if (overload_cnt1 < 6) tx <=#Tp 1'b0; else tx <=#Tp 1'b1; end else if (error_frame) // 传输错误帧 begin if (error_cnt1 < 6) begin if (node_error_passive) tx <=#Tp 1'b1; else tx <=#Tp 1'b0; end else tx <=#Tp 1'b1; end else tx <=#Tp 1'b1; end end always @ (posedge clk) begin if (tx_point) tx_q <=#Tp tx & (~go_early_tx_latched); end //延迟发送数据 always @ (posedge clk) begin tx_point_q <=#Tp tx_point; end 复制代码 0
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