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将Vivado HLS与Virtex 6（ML605评估套件）一起使用时，我遇到以下问题。
我想导出一个RTL Designas Pcore，以便稍后将其导入XPS作为完整设计的一部分。 根据相对视频（2:40），必须获得Vivado独立版（许可证VIVADO_HLS）。 我下载并安装了Vivado HLS系统版，并通过Vivado License Manager免费试用30天进行了许可。 但是，当我在Vivado HLS中创建一个新项目（针对Virtex 6）并尝试在“C Synthesis”之后执行“Export RTL”时，“格式选择”下拉菜单中没有“Pcore for EDK”选项 。 此外，当我运行Co-Simulation时，我收到以下错误： 错误：[COSIM 212-4] *** C / RTL协同仿真完成：FAIL ***（DEBUG） - > vhdl_sim_run {...} @“autosim.tcl”=>错误：“运行Vivado失败”（ DEBUG） - > - > prepare_ip {{vhdl}} @“autosim.tcl”=>错误：“运行Vivado失败”错误：[Coretcl 2-106]无法找到指定的部分。 以上似乎暗示指定的电路板（Virtex 6）不受支持，即使在上面的视频中澄清了Vivado HLS确实支持带有VIVADO_HLS许可证的Virtex 6。 我的问题是，我如何获得Vivado独立版（许可证VIVADO_HLS）以运行协同仿真并将RTL导出为XPS作为Pcore？ 非常感谢你提前。 以上来自于谷歌翻译 以下为原文 I have the following issue when using Vivado HLS with Virtex 6 (ML605 Evaluation Kit). I want to export an RTL Design as Pcore in order to import it later to XPS as part of a complete design. According to the relative video (at 2:40), a Vivado standalone (licence VIVADO_HLS) must be obtained. I downloaded and installed the Vivado HLS System Edition and licensed it with a free 30 day trial from the Vivado License Manager. However, when I create a new project in Vivado HLS (targeted to a Virtex 6) and try to perform "Export RTL" after "C Synthesis", the option "Pcore for EDK" is not available under "Format Selection" drop down menu. Moreover, when I run Co-Simulation I get the following error: ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL *** (DEBUG) -> vhdl_sim_run{...} @ "autosim.tcl" => ERROR: "Run Vivado failed" (DEBUG) -> -> prepare_ip{{vhdl}} @ "autosim.tcl" => ERROR: "Run Vivado failed" ERROR: [Coretcl 2-106] Specified part could not be found. The above seems to imply that the specified board (Virtex 6) is not supported even though it is clarified in the above video that Vivado HLS does support Virtex 6 with the VIVADO_HLS license. My question is, how can I obtain the Vivado stand-alone (license VIVADO_HLS) in order to run Co-Simulation and export the RTL to XPS as Pcore? Thank you very much in advance. 
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@jafou
Virtex 6支持到Vivado HLS 2015.4。 请改用此版本。 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 @jafou Virtex 6 is supported till Vivado HLS 2015.4. Please use this version instead. Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark).View solution in original post |
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@jafou
您使用的是哪个版本的Vivado HLS？ 请在此处分享您的许可文件和xinfo。 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 @jafou Which version of Vivado HLS are you using? Please share your license file and xinfo here. Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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@nupurs
我正在使用Vivado HLS 2016.4系统版。 下面我附上30天试用许可证和购买的许可证。 这些都没有为我提供将RTL导出为“Pcore for EDK”的选项。 由于我是FPGA和Xilinx工具的新手，所以我们非常感谢您的帮助。 trial.lic 1 KB Xilinx.lic 2 KB xinfo.txt 122 KB 以上来自于谷歌翻译 以下为原文 @nupurs I am using Vivado HLS 2016.4 System Edition. Below I am attaching both the 30 day trial license and the purchased one. Neither of these provides me with the option of exporting the RTL as "Pcore for EDK". Since I am very new to FPGAs and Xilinx Tools, any help is appreciated. |
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@jafou
Virtex 6支持到Vivado HLS 2015.4。 请改用此版本。 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 @jafou Virtex 6 is supported till Vivado HLS 2015.4. Please use this version instead. Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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@nupurs非常感谢你的回复。
我将使用您提到的版本。还有一件事，如何在30天试用期结束后获得VIVADO_HLS许可证？ 我之前附加的许可证是否支持HLS中的Virtex 6？再次感谢您的快速回复。 以上来自于谷歌翻译 以下为原文 @nupurs Thank you very much for your reply. I will use the version you mentioned. Just one more thing, how can I obtain the VIVADO_HLS license after the 30 day trial expires? Does the license I attached previously support Virtex 6 in HLS? Again, thank you for your quick reply. |
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@jafou，
是的，您附带的许可证支持Virtex-6。 如果您需要其他试用许可证（但我认为您拥有的其他许可证已足够），那么您可以通过以下链接联系FAE：https：//www.xilinx.com/about/contact/authorized-distributors.html 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 @jafou, Yes, the license you attached supports Virtex-6. In case you need another trial license(but I think the other license you have is enough), then you can contact an FAE from this link: https://www.xilinx.com/about/contact/authorized-distributors.html Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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@nupurs
它似乎与2015.4版本一起使用，因为“Pcore for EDK”现在可作为选项提供。 非常感谢您的帮助。 我仍然在Co-Simulation期间得到了跟随镜（C-Synthesis过程正常）： 错误：[VRFC 10-149]'floating_point_v6_1'未在库xilinxcorelib中编译[D：/FPGA_Projects/HLS/sobi_covariance/solution1/sim/vhdl/ips/fadd_v6.vhd:72] 错误：请检查在'xelab'期间创建的快照名称，当前快照名称“xsim.dir / sobi_covariance / xsimk.exe”不存在 @E [SIM-4] *** C / RTL协同模拟完成：失败*** 问题是，上述错误仅在我运行Co-Simulation for Virtex 6时出现。如果使用Zynq ZC702作为目标板创建同一项目的另一个解决方案，则不会发生错误。上述内容与许可证有关 ，还是一个完全不相关的问题？ 如果是后者，我应该在另一个主题中发布一个问题。 非常感谢您的宝贵时间。 你的帮助非常有用。 以上来自于谷歌翻译 以下为原文 @nupurs It seems to work fine with the 2015.4 version since the "Pcore for EDK" is now available as an option. Thank you very much for your help. I still get the following errors during Co-Simulation though (the C-Synthesis process works fine): ERROR: [VRFC 10-149] 'floating_point_v6_1' is not compiled in library xilinxcorelib [D:/FPGA_Projects/HLS/sobi_covariance/solution1/sim/vhdl/ips/fadd_v6.vhd:72] ERROR: Please check the snapshot name which is created during 'xelab',the current snapshot name "xsim.dir/sobi_covariance/xsimk.exe" does not exist @E [SIM-4] *** C/RTL co-simulation finished: FAIL *** The thing is, that the above errors only appear when I run Co-Simulation for Virtex 6. If I create another solution of the same project with a Zynq ZC702 as the targeted board, no errors occur. Does the above have anything to do with the licenses, or is it a completely irrelevant issue? If it's the latter, I should probably post a question in a different topic. Thank you very much for your time. Your help has been more than useful. |
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@nupurs
我注意到我在上面发布的错误（使用Vivado模拟器时出现）在为协同仿真选择ISE模拟器时更改为以下内容： @E [SIM-119]找不到ISIM。 确保将其添加到路径变量中。 我试过这个模拟器，因为我假设ISE用于验证针对旧设备的设计。 以上来自于谷歌翻译 以下为原文 @nupurs I noticed that the error that I posted above (which appears when using Vivado Simulator), changes to the following when choosing ISE Simulator for the Co-Simulation: @E [SIM-119] Cannot find ISIM. Make sure it is added to the path variable. I tried with this simulator because I assumed that ISE is used for validating designs targeted for older devices. |
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通过将PATH变量指向Xilinx实现工具，我在使用ISE Simulator时解决了协同仿真问题：
https://www.xilinx.com/support/answers/43271.html 有没有办法解决Virtado模拟器与Virtex 6的问题？ 或者是否无法将此模拟器与较旧的设备（如Virtex 6）一起使用？ 我问，因为这个选项似乎更快。 以上来自于谷歌翻译 以下为原文 I solved the Co-Simulation problem when using ISE Simulator by pointing the PATH variable to Xilinx implementation tools according to: https://www.xilinx.com/support/answers/43271.html Is there a way to solve the problem regarding the Vivado Simulator with Virtex 6? Or is it not possible to use this simulator with an older device such as Virtex 6? I am asking because this option seems to be faster. |
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@jafou，
Vivado仅支持7系列和Ultrascale设备。 所以我担心使用Vivado模拟器是不可能的。 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 @jafou, Vivado supports only 7 series and Ultrascale devices. So I am afraid using the Vivado Simulator is not possible. Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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