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VHDL中的二维数组怎么实现

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问答对人有帮助，内容完整，我也想知道答案 0 亲爱的用户，我想在VHDL中实现二维数组（内存），并希望通过各种组件访问（读取）它，其中一个组件（用于读取和写入）都在verilog中。任何人都可以建议我声明一个模块及其与各种组件的链接。有害生物风险分析有害生物风险分析以上来自于谷歌翻译以下为原文 Dear users, I want to implement a two dimensional array (memory) in VHDL, and want to access (read ) it through various components, one of the components (both for reading and writing)is in verilog. Can anyone suggest me a way to declare a module and its linkage to various components. Pras Pras 0
2019-1-23 08:25:21　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答举报冯虎虔相关推荐 • labview按行读取二维数组之后再按读取顺序重新组成二维数组如何实现？ 4124 • labview 一个二维数组分别与50个二维数组做运算，输出最小值 4583 • 二维数组怎么转化为簇 10250 • 一维数组写入二维空数组 3549 • LabVIEW中怎样将一维数组转换成二维数组 90171 • 将一个二维数组里面的元素从大到小排列是不是只能先变成一维数组排序? 4342 • 二维数组怎么能够在自选的路径中直接生成EXCEL表格 4085 • labview二维数组提取几行组成新数组 19758 • 如何在labview中实现二维DFT? 3297 • labview二维数组索引按顺序输出一维数组？ 6257 11个回答

答案对人有帮助，有参考价值 0 如果可能的话，坚持使用一个HDL会更容易。 ------------------------------------------“如果它不起作用模拟，它不会在板上工作。“ 以上来自于谷歌翻译以下为原文 It would be easier to stick to one HDL if at all possible. ------------------------------------------ "If it don't work in simulation, it won't work on the board."

2019-1-23 08:44:21 评论举报李刚

答案对人有帮助，有参考价值 0 好。但是从顶层文件中访问其他组件的内存（数组）的过程是什么？有害生物风险分析有害生物风险分析以上来自于谷歌翻译以下为原文 Ok. But what is the procedure to access the memory (array) in the top file from other components? Pras Pras

2019-1-23 08:51:58 评论举报曹阳

答案对人有帮助，有参考价值 0 我不确定你实际上在做什么以及在什么情况下。在VHDL中你不能通过其实体的端口访问其他架构内的信号。 Verilog不是那么严格。假设VHDL，你需要设计访问结构，使你能够编写和读取内存数组。或者您可以使用LogiCore构建一个内存组件，其中定义了端口和使用情况。您之前是否完成了数字设计？ ------------------------------------------“如果它不起作用模拟，它不会在板上工作。“ 以上来自于谷歌翻译以下为原文 I'm not sure what you are actually trying to do and in what context. In VHDL you cannot access signals inside other architectures except via their entity's ports. Verilog is not so strict. Assuming VHDL, you need to design access structures to enable you to write and read the memory array. Or you could use LogiCore to build you a memory component that has the ports and usage thereof defined. Have you done digital design before? ------------------------------------------ "If it don't work in simulation, it won't work on the board."

2019-1-23 09:00:46 评论举报李刚

答案对人有帮助，有参考价值 0 你在vhdl的经历是什么？你能写一个矢量模块吗？以上来自于谷歌翻译以下为原文 what is your experiance in vhdl ? can you write a single vector module ?

2019-1-23 09:09:28 评论举报张磊

答案对人有帮助，有参考价值 0 VHDL可能允许您在组件的端口中具有二维数组。 Verilog不允许在端口中使用多维数组。所以通常的方法是定义一个行为就像的二维数组可能是分布式或块式RAM（取决于它有多大以及如何使用）多端口。然后运行地址和数据端口（不是数组本身） RAM到模块端口。包含RAM的模块是VHDL还是Verilog并不重要。该重要的一点是拥有所有内存访问的行为代码（地址和数据端口，以及读写过程）在内存模块中被定义为。您可以从语言模板或XST手册中获取此信息。 - Gabor - Gabor 以上来自于谷歌翻译以下为原文 VHDL probably allows you to have two dimensional arrays in the component's ports. Verilog does not allow multidimensional arrays in ports. So the usual method is to define a two-dimensional array that behaves just like distributed or block RAM (depending on how big it is and how it's used), possibly multiported. Then run the address and data ports (not the array itself) of the RAM to the module ports. It doesn't really matter whether the module containing the RAM is VHDL or Verilog. The important point is to have all of the behavioral code for memory access (the address and data ports, and read and write processes) in the module where the memory is defined. You can get this from the language templates or the XST manual. -- Gabor -- Gabor

2019-1-23 09:24:34 评论举报杨玲

答案对人有帮助，有参考价值 0 亲爱的用户，我是FPGA的新手。我在verilog做了一些程序。 VHDL我是第一次尝试。我担心的是我们如何将内存带到实体端口？这也必须用作输入（许多组件）和输出（对于一个comp，用于写入目的）。在verilog中，我能够简单地访问内存 REG1 以下为原文 Dear users,I am new to FPGAs. I have made some programs in verilog. VHDL I am trying for the first time.My concern is how can we bring the memory to entity port? That too has to be used as input (many components) and output(for one comp, for writing purpose). In verilog I was able to access the memory simply asreg1<=memory[address]; that too inside a single module.I am confused how to bring this memory at port, there may be too many wires to connect to diff modules/entity.Again I can go for declare as many vectors/reg as memory elements, but the problem is same how to bring them all at the port?Please provide me a direction.PrasPras

2019-1-23 09:40:07 评论举报曹阳

答案对人有帮助，有参考价值 0 如果您有一些Verilog的经验，为什么需要/想要切换到VHDL？如果你能在Verilog中做到这一点，那就在Verilog中做吧！ ------------------------------------------“如果它不起作用模拟，它不会在板上工作。“ 以上来自于谷歌翻译以下为原文 If you have some experience in Verilog, why do you need/want to switch to VHDL? If you can do it in Verilog, do it in Verilog! ------------------------------------------ "If it don't work in simulation, it won't work on the board."

2019-1-23 09:56:16 评论举报李刚

答案对人有帮助，有参考价值 0 mishra.pras写道：亲爱的用户，我是FPGA的新手。我在verilog做了一些程序。 VHDL我是第一次尝试。我担心的是我们如何将内存带到实体端口？这也必须用作输入（许多组件）和输出（对于一个comp，用于写入目的）。在verilog中，我能够简单地访问内存 REG1 这实际上是硬件设计问题，而不是语言问题。如果你不想要合成生成数千个触发器来构建你需要遵守规则的“记忆” 可用内存结构（单端口或双端口，分布式或块RAM）。记忆本身应始终包含在一个模块（或组件）中。那个模块需要有所有对reg1端口的内存阵列的直接访问模块的内存是端口（addr_a，addr_b，din_a，din_b，dout_a，dout_b ......）不是内存数组本身。正如我在之前的文章中所说，你可以找到用于推理的VHDL（或Verilog）模板语言模板中的所有可用内存类型以及XST用户手册。因此，如何将存储器阵列连接到模块（组件）端口的简短答案是不要这样做。虽然在VHDL中允许它，但您无法从Verilog和综合中访问它工具不会推断记忆，而是大量的触发器。 - Gabor - Gabor 以上来自于谷歌翻译以下为原文 mishra.pras wrote: Dear users,I am new to FPGAs. I have made some programs in verilog. VHDL I am trying for the first time.My concern is how can we bring the memory to entity port? That too has to be used as input (many components) and output(for one comp, for writing purpose). In verilog I was able to access the memory simply asreg1<=memory[address]; that too inside a single module.I am confused how to bring this memory at port, there may be too many wires to connect to diff modules/entity.Again I can go for declare as many vectors/reg as memory elements, but the problem is same how to bring them all at the port?Please provide me a direction.Pras This is really a hardware design issue, not a language issue. If you don't want synthesis to generate thousands of flip-flops to build your "memory" you need to abide by the rules of the available memory structures (single or dual port, distributed or block RAM). The memory itself should always be contained within one module (or component). That module needs to have all of the direct access to the memory array as in reg1<=memory[address]; The ports of the module are the ports of the memory (addr_a, addr_b, din_a, din_b, dout_a, dout_b ...) not the memory array itself. As I said in the earlier post, you can find VHDL (or Verilog) templates for inference of all available memory types in the language templates as well as the XST user manual. So the short answer of how to attach the memory array to module (component) ports is don't do it. While it is allowed in VHDL, you can't access it from Verilog, and the synthesis tools will not infer memory, but rather tons of flip-flops. -- Gabor -- Gabor

2019-1-23 10:11:52 评论举报杨玲

答案对人有帮助，有参考价值 0 亲爱的用户，我写了一个vhdl程序来编写和读取内存。我成功了。然后我将这个vhdl文件作为组件添加到另一个verilog程序中。我试图使用地址和数据线访问the vhdl组件。但在综合过程中，它显示了数据信号上多源的错误。虽然这个数据信号是vhdl程序的输出，并且仅用作输入。由于verilog和vhdl的混合，这个问题。有害生物风险分析以上来自于谷歌翻译以下为原文 Dear users, I wrote a vhdl programme to write and read memory. I did it successfully. Then I added this vhdl file as a component to another verilog program. I tried to acces theis vhdl component using address and data lines. But during synthesis it displayed error of multisourcing on the data signal. Though this data signal is output of the vhdl programme and is being used as an input only. Is this problem due to the mixing of verilog and vhdl.Pras

2019-1-23 10:27:14 评论举报曹阳

答案对人有帮助，有参考价值 0 你好我会在这里直言不讳抱歉你离基地很远。离开基地的方式。不要混合语言，这是真的，但这不是基本功能，这是你在vhdl / verilog中没有足够的经验，而你似乎正以同样的方式接近描述语言你会像C ++一样进行堆叠过程。你需要退后一步思考，以上来自于谷歌翻译以下为原文 Hi I'm going to be blunt here, sorry you are way off base. way way off base. don't mix languages, that is true, but that is not the basic feature, it's that you are not experianced enough in vhdl / verilog, and you seem to be approaching a description language in the same way you would a stack process like C++. you need to take step back me thinks,

2019-1-23 10:41:51 评论举报张磊

答案对人有帮助，有参考价值 0 >我写了一个vhdl程序来写和读内存。我成功了。实际上，您创建了VHDL设计。您没有创建正在创建硬件设计的“程序”。 >然后我将这个vhdl文件作为组件添加到另一个verilog程序中。实际上，您在另一个Verilog设计中将VHDL设计添加为组件或子模块。 >我试图使用地址和数据线访问the vhdl组件。您正在创建硬件而不是软件，因此您无法访问先前创建的VHDL读/写内存设计。 Verilog设计将通过为地址，数据和时钟提供必要的硬件信号来控制VHDL设计，并使用Verilog设计其他部分的数据输出作为回报。 >但是在合成期间，它显示数据信号上的多源的错误。虽然这个数据信号是 >正在进行vhdl程序的输出仅用作输入。当合成器报告网络有多个源时，意味着您的HDL中有两个点正在尝试更改网络状态。您需要重新检查HDL源以确定发生的位置。我的猜测是，这是因为你正在尝试做一些在实际设计中不实用的东西。回到这个线程的开头，你说你想要一个可以从设计中的许多地方访问的单个二维存储器阵列。这个概念适用于在CPU上运行的软件，但您不是在设计正在设计硬件的软件。您正在创建的硬件同时运行所有电路，而软件按顺序运行每个指令。如果您有10个模块，每个模块都想要读取或写入内存阵列，那么这意味着您需要一个10端口内存。在FPGA中创建10端口存储器是不实际的，但如果需要可以完成。您需要创建一个内存模块，其中包含10个端口，每个端口都带有地址，data_in，data_out和读/写，以便执行此操作。 >这个问题是由于verilog和vhdl的混合造成的。不，是因为你的设计错了。 ------您是否尝试在Google中输入问题？如果没有，你应该在发布之前。太多结果？尝试添加网站：www.xilinx.com 以上来自于谷歌翻译以下为原文 > I wrote a vhdl programme to write and read memory. I did it successfully. Actually, you created a VHDL design. You are not creating "programs" you are creating a hardware design. > Then I added this vhdl file as a component to another verilog program. Actually, you added the VHDL design as a component or sub-module in another Verilog design. > I tried to acces theis vhdl component using address and data lines. You are creating hardware and not software, so you are not accessing the VHDL read/write memory design that you created earlier. The Verilog design would be controlling the VHDL design by providing the necessary hardware signals for address, data and clock and in return using the data output in other parts of the Verilog design. > But during synthesis it displayed error of multisourcing on the data signal. Though this data signal is > output of the vhdl programme and is being used as an input only. When the synthesizer reports that a net has multiple sources it means that you have two points in your HDL that are trying to change the state of the net. You will need to re-examine your HDL source to determine where this occuring. My guess is that this is occuring because you are trying to do something that is not practical in a real design. Way back at the beginning of this thread you stated that you wanted to have a single two dimensional memory array that can be accessed from many places within the design. This concept works with software running on a CPU, but you are not designing software you are designing hardware. The hardware that you are creating runs everything circuit at the same time time, while software runs each instruction sequentially. If you have 10 modules that each want to read or write the memory array then that means that you need a 10 port memory. Creating a 10 port memory is not practical in an FPGA, but can be done if needed. You will need to create a memory module that has 10 ports each with address, data_in, data_out and read/write in order to do this. > Is this problem due to the mixing of verilog and vhdl. No it is because your design is wrong. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com

2019-1-23 10:53:19 评论举报李森

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