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而verilog代码是：
=======================================
模块zero_detect（clk，signal_in，trig_out）;
输入clk，signal_in;
输出trig_out;
reg signal_d;
永远@（posedge clk）
signal_d 以下为原文
Yes you can use this circuit.
And the verilog code is :
=======================================
module zero_detect(clk,signal_in,trig_out);
input clk,signal_in;
output trig_out;
reg signal_d;
always @(posedge clk)
signal_d <= signal_in;
assign trig_out = signal_in ^ (~signal_d);
endmodule
=======================================
Be careful about your voltage comparator's output signal range. It must within the FPGA's input voltage range.
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