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我的系统由FPGA和FX3组成。
将pKTANKα单插入到数据的最后一个字，每个FX3缓冲器的SIZEF设置为16KB。 我不知道为什么那台PC什么也没收到，当我发送多个1KB数据，但小于16KB，从FPGA到FX3。 有人告诉我，当每个FX3缓冲区的大小被设置时，我如何发送多个1KB数据，但小于16KB？ 16kb。 谢谢 以上来自于百度翻译 以下为原文 My system is composed with FPGA and FX3. The PKTEND# single was inserted along with the last word of data, and the sizeof of every FX3 buffer was set 16KB. I don't know why that PC received nothing, when i sent multiple of 1KB data ,but smaller than 16KB, from fpga to FX3. Can somebody tell me how can i send multiple of 1KB data ,but smaller than 16KB,when the sizeof of every FX3 buffer is set 16KB. Thanks 
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你好，
请在www. CyPress网站上创建技术支持案例。我们的工程师可以帮助你通过。我相信我们可能已经研究了这个项目并尝试在这里复制它。 当做， 加亚特里 以上来自于百度翻译 以下为原文 Hi, Please create tech support case at www.cypress.com -> Support -> Technical support. One of our engineers can assist you through. I believe we may have look into the project and try replicating it here. Regards, Gayathri |
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您好，请参见CyPress EZ-USB FX3 SDK发行说明，版本1.3（FX3RelaseNotes .pdf）中的“已知问题”9。发送ZLP可能会导致传输错误（不幸的是，它没有描述什么类型的错误）。你可以尝试在USB数据包之间进行巨大的停顿。我个人会避免发送ZLP。如果可能的话，发送一些虚拟数据代替。或拆分最后一个完整的数据包。卡莱夫
以上来自于百度翻译 以下为原文 Hi, See "known issue" 9 in Cypress EZ-USB FX3 SDK Release Notes, Version 1.3 (FX3ReleaseNotes.pdf). Sending ZLP may cause transfer errors (unfortunately it's not described what kind of errors). You could try with huge pauses between USB packets. I personally would avoid sending ZLP. If possible, send some dummy data instead. Or split the last full packet. br, kalev |
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你好，
我试着在USB数据包之间有足够的暂停，但是它仍然是一样的。 我试图创造一个案件，但网络显示“你不能访问这个应用程序。”请与网站管理员@ CyPress网站联系。 以上来自于百度翻译 以下为原文 Hi, I tried with enough pauses between USB packets,but it was still the same. I tried to creat a case but the web shown that " You do not have access to this application. Please contact webmaster@cypress.com". |
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要创建TS案例，请遵循以下步骤：
1）登录CY网站。 2）去支持和社区-技术支持-创建一个案例 3）提供细节。 当做， -马迪 以上来自于百度翻译 以下为原文 To create a TS case, please follow these steps : 1) Login into CY website. 2) go to Support and Community -> Technical Support -> Create a MyCase 3) Provide the details. Regards, -MADY |
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我是从同一个问题来的。任何1024字节的偶数倍数从FPGA发送到USP3，但PC没有接收到任何错误。如果我发送少于或多于1024字节的倍数，一切都很好。在每种情况下，当发送最后4个字节（使用32位接口）时，设置PKKNADE。
另一个问题是当发送16384个字节（Max PKTStand）时，这会在PC机上造成错误。 如果它是一个精确的帧大小（1024字节的倍数），是否可以用PKTACK集发送最后一个数据？这是一个我还没有测试过的案例。 以上来自于百度翻译 以下为原文 I have come accross the same issue. Any even multiple of 1024 bytes is sent to the USB3 from an FPGA, but nothing is received by the PC. There are no errors. If I send less than or more than a multiple of 1024 bytes, everything works fine. In each case, PKTEND is set when sending the last 4 bytes (using 32 bit interface). Another issue is when sending 16384 bytes (MaxPktSize), but this causes an error on the PC. Is it possible that sending the last data with PKTEND set causes an issue if it is an exact frame size (multiple of 1024 bytes)? This was one case I haven't yet tested. |
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大家好，
通过暴力实验和没有帮助的任何文件，我想出了如何写多字节的1024字节的包倍数到FX3在同步从FIFO模式。基本上是这样的，假设32位模式。 1）通过断言SLCSWN＝0和SLWRYN＝0来写字1～255。 2）用SLCSYN＝0和SLWRYN＝0写入Word 256（或1024字节的任意多个字节是您的总流长度）。保持PkTrangnn＝1！ 3）等待4 GPIF时钟周期。 4）断言PKTrangnn＝0正好是一个时钟周期来创建ZLP。 5）在做任何其他事情之前，等待4个时钟周期。 以上来自于百度翻译 以下为原文 Hi everyone, Through brute force experimentation and no help from any of the documentation I figured out how to write multiples of 1024 byte packet multiples to FX3 in synchronous slave FIFO mode. It basically goes like this, assuming 32-bit mode. 1) Write words 1 - 255 by asserting slcs_n = 0 and slwr_n = 0. 2) Write word 256 (or whatever multiple of 1024 bytes is your total stream length) with slcs_n = 0 and slwr_n = 0. Keep pktend_n = 1 ! 3) Wait for 4 GPIF clock cycles. 4) Assert pktend_n = 0 for exactly one clock cycle to create a ZLP. 5) Wait 4 more clock cycles before doing anything else. |
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这对于1kb倍数非常有效，除非它达到16kb（fx3缓冲区大小）。有没有人从一个从FIFO接口发送一个16KB（16384字节）数据包到PC的解决方案？
以上来自于百度翻译 以下为原文 This works great for 1kB multiples except when it reaches 16kB (FX3 Buffer Size). Does anyone have a solution for transmitting a single 16kB (16384 bytes) packet from the Slave FIFO interface all the way to the PC? |
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我已经改变了状态机（使用GPIF II），并消除了所有“镜像状态”，稍微改变了协议。这些数据包现在起作用，正如我预期它们的功能（即小于一个完整的数据包，发送PKKActive活动，同时写入到最后的32位字，没有ZLP跟随）。对于精确的数据包大小，在写入时发送最后一个32位字，PKCADE不活动，然后等待一段短时间并编写ZLP）。这工作可靠地从从端口向PC发送64K字节。在不等待的情况下发送多个16K字节分组仍然存在问题，或者在下一个传输块的开始时释放多个32位字。
另一个问题是发送大量少于16K字节的传输，这取决于传输的大小。 我已经附加了状态机图。 PNG 70 K 以上来自于百度翻译 以下为原文 I have changed the State Machine (using GPIF II) and have eliminated all "Mirrored States" which changed the protocol slightly. The packets now work as I would expect them to function (ie less than a full packet, send PKTEND active while writting to the last 32-bit word with no ZLP following. For exact packet size, send last 32-bit word with PKTEND inactive while writing, then wait a short time and write a ZLP). This works for reliably sending up to 64K Bytes from the Slave Port to the PC. There is still an issue in sending multiple 16K Byte packets back to back without waiting or you loose multiple 32-bit words at the beginning of the next block of transfers. Another issue is with sending a lot of transfers with less than 16K Byte back to back, and it is dependant on the size of the transfers. I have attached the State Machine Diagram.
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嗨半履带，和……然后等待一个短时间写一个ZLP你不应该依赖时间。相反，您应该检查GPIF标志。如果没有空闲缓冲区就绪，就不能写入FX3中的任何数据（包括初始化ZLP）。
参见FX3RelaseNoto.PDF中已知的第9个问题——发送ZLP可能会导致数据传输错误。 请注意，这是不容易保证足够的暂停ZLP和后续数据包，这是建议的塞浦路斯。根据USB协议，主机对管内数据包进行轮询。虽然您在FX3中发起ZLP的发送，但主机可能稍后会开始对该分组进行轮询/接收。根据主机应用程序和CPU上的负载，暂停可能超过几十秒。而且，即使主机开始对ZLP进行轮询，USB电缆中的错误仍然可能导致该ZLP在电缆上进行多次轮询/重新发送。 为了在FX3中构建防弹工作区，你应该能够确定什么时候FX3在USB电缆上完成这个ZLP的发送。可能更容易在主机应用程序中解决这个问题——如果ZLP被接收到，那么在下一次读之前暂停一点（我还没有验证这个解决方案）。 如果你事先知道数据长度（好像是你的情况），那么你可以避免通过将最后的完整数据包分割成两个短数据包来发送ZLPS。 卡莱夫 以上来自于百度翻译 以下为原文 Hi halftrack, > ...then wait a short time and write a ZLP You should not rely on timings. Instead, you should check GPIF flags. You cannot write any data (including initiating ZLP) into FX3 if there is no free buffer ready. See also known issue #9 in FX3ReleaseNotes.pdf - sending ZLP may cause data transfer errors. Note that it's not easy to guarantee enough pause between ZLP and subsequent data packet as this is suggested by Cypress. According USB protocol, host polls for IN pipe packets. Although you initiate sending of ZLP in FX3, host may start polling/receiving of this packet significantly later. Depending on host application and load on CPU, pause may exceed tens of seconds. And even if host starts polling of this ZLP, still errors in USB cable may cause this ZLP to be re-polled/re-sent over cable several times. To build bulletproof workaround in FX3, you should be able to determine when exactly FX3 finishes sending of this ZLP over USB cable. Probably it's easier to solve this issue in host application - pause a bit there before starting next read if ZLP is received (I have not verified this solution). If you know data length beforehand (as it seems to be your case) then you can avoid sending ZLPs just by splitting last full packets into two Short Packets. br, kalev |
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卡列夫
谢谢你的回复。我已经正确地增加了写零长度包以满足125U之后的延迟，而我一直使用DMA标志来确保只有在标志有效时才写入。当您编写一个完整的缓冲器（16384字节）时，出现一个问题，即它没有正确地设置DMA标志，这就是为什么我在完全写入缓冲区之后需要等待的原因。如果在发送零长度包之前，我不等待写完整缓冲区之后，数据的完整缓冲区就丢失了。如果我写1个字小于完整的缓冲区大小，所有的工作都很好，发送一个短的数据包（PKTAN在最后一次写入时是活动的）。我知道这不是一个正确的使用，但问题是柏树FX3，这是唯一的解决方案，似乎提供某种程度的操作！ 我会感激任何信息，可以更好地解决这个问题。如果你找到一个可行的解决方案，请告诉我。 注意：使用专用DMA标志到“DMA线程3准备好”。这就是我所相信的，当两位地址为“11”时，用于写入DMA引擎的标记为散列。 斯科特 以上来自于百度翻译 以下为原文 Kalev Thanks for the response. I have correctly increased the delay after writing a Zero Length Packet to meet the 125uS and I have always been using the DMA Flags to ensure writing only when the flags are valid. There is an issue when you write a full buffer (16384 bytes) that appearantly does not set the DMA flag properly and this is why I need a wait after fully writing to the buffer. If I don't wait after writing a full buffer before I send the Zero Length Packet, the full buffer of data is lost. If I write 1 word less than the full buffer size, everything works fine with sending a short packet (PKTEND is active during last write). I understand this is not a proper use, but the issue is with the Cypress FX3 and this was the only solution that appears to provide some level of operation! I would appreciate any information that may solve this issue in a better way. Please tell me if you find a working solution. Note: Using dedicated DMA Flags to "DMA Thread 3 Ready". This is what I believe is my Bulk In Flag to use for writing to the DMA engine when the two bit address is "11". Scott |
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嗨，史葛，我一直在设计缓冲区边界，但是我从来没有碰到过数据丢失。与你不同，我不使用GPIF地址线。控制地址有什么不对吗？我使用thRead 0xDMAYRADE和THEADRY00DMAX水印标志来确定是否允许写入FX3缓冲区。虽然thuly00dMAX水印和thRead 0xDMAYRADE都被断言（即在缓冲器中有大量空闲空间），然后我在每个时钟前端写入突发模式下的数据项。当thRead 00dMAX水印被撤销（缓冲区几乎满了）之后，我在每个写一次之后等待几个时钟周期，让thRead 00dMAYRADE准备好缓冲/反映缓冲状态。如果THEADRY00DMAYADED仍然保持声明，则写入下一个数据项。等等，我也从来没有生成ZLPS。有了这样的实现，我从未见过数据丢失。如果我在写一个完整的缓冲区之前不等待，我发送零长度包，数据的完整缓冲区就丢失了。发送ZLP是数据丢失的关键吗？如果你继续发送数据而不插入ZLP，它有效吗？关于ZLP后的125US延迟。在GPIF侧写入时是否插入此延迟？ZLP已知问题是指FX3与主机之间USB通信中的时序问题。不能从GPIF侧可靠地控制USB时序。使用FX3DMA回调，您可以验证缓冲区与哪些数据从GPIF传递到USB，这样您就可以确定数据是否在GPIF或USB侧丢失。卡莱夫
以上来自于百度翻译 以下为原文 Hi Scott, I write across buffer boundaries in my design all the time but I have never hit data loss. Differently from you, I do not use GPIF address lines. Could it be that there is something wrong in controlling addresses? I use Thread_0_DMA_Ready and Thread_0_DMA_Watermark flags to determine whether the write to FX3 buffer is allowed or not. While Thread_0_DMA_Watermark and Thread_0_DMA_Ready both are asserted (i.e. there is a lot of free space in buffer) then I write data items in burst mode at each clock front. When Thread_0_DMA_Watermark gets deasserted (buffer is almost full) then I wait several clock cycles after every single write to let the Thread_0_DMA_Ready to settle down/reflect buffer state. If Thread_0_DMA_Ready still keeps asserted, I write next data item. Etc. I also never generate ZLPs. With such an implementation I have never seen data loss. > If I don't wait after writing a full buffer before > I send the Zero Length Packet, the full buffer of data is lost. Is sending ZLP the key for data loss? If you continue sending data without inserting ZLP, does it work? About this 125us delay after ZLP. Are you inserting this delay between writes in GPIF side? ZLP known issue refers to the timing problem in USB communication between FX3 and Host. You can't control USB timings reliably from GPIF side. With FX3 DMA callbacks you can verify what the buffers with what data are delivered from GPIF to USB, so that you can determine whether the data gets lost in GPIF or USB side. br, kalev |
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卡列夫
当你精确写1个缓冲区大小（这是16384个字节，或者在我的情况下是2048个32位字）时，你可能想验证一切都很好。我唯一的问题是写1个缓冲区大小的精确倍数。 我可以写任何数量，除了缓冲区大小的精确倍数，一切都很好。 如果我写1X，2X，或3X的缓冲区大小，有数据丢失的数据发送。（除非我在写零长度包之前延迟） 如果我写4x缓冲区大小（最终是65536字节），这很好。我不知道为什么这样做。 溴 斯科特 以上来自于百度翻译 以下为原文 kalev You might want to verify everything works fine when you write exactly 1 buffer size (this is 16384 bytes or 2048 32-bit words in my case). The only time I have an issue is writing exact multiples of 1 buffer size. I can write any amounts, except exact multiples of the buffer size, and everything works fine. If I write exactly 1x, 2x, or 3x the buffer size, there is data loss of the data sent. (unless I delay before writing the zero length packet) If I write exactly 4x the buffer size (ends up being 65536 bytes), this works fine. I am not sure why this works. br Scott |
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嗨，史葛，我猜你在主机上执行64K字节的读取。然后，当FX3发送64K字节的数据时，整个主机缓冲区就得到满足并返回到应用程序。见我的帖子在上面的24 OCT 2013。如果在主机中执行64K读取，并且传输4X缓冲区大小16K数据成功，那么我相信您正确地检查GPIF标志。否则，某些数据在从一个缓冲区切换到另一个缓冲区时会丢失。如果发送1X、2X或3X缓冲区大小的数据，则分别在第二、第三或第四缓冲区中生成ZLP。如果缓冲区变为可用（即标志指示缓冲区为空），那么数据丢失吗？如果你再等待一点，然后生成ZLP，那么传输成功了吗？顺便问一下，你要等多少？因此，根据您的测试，无论是将数据写入缓冲区还是生成ZLP，都存在显著差异。数据可以即时写入，ZLP不是吗？读取操作如何在主机中完成？它是否以成功代码返回，只是数据比预期少？卡列夫
以上来自于百度翻译 以下为原文 Hi Scott, I guess you perform 64K byte reads in host. Then, when FX3 has sent 64K bytes of data, the entire host buffer gets fulfilled and is returned to your application. See my post on 24 Oct 2013 above. If you perform 64K reads in host and transferring of 4x buffer size 16K data succeeds, then I believe that you check GPIF flags correctly. Otherwise some data should get lost during switching from one buffer to another. If you send 1x, 2x, or 3x buffer sizes of data, you generate ZLP respectively in 2nd, 3rd, or 4th buffer. Do you state that if you generate this ZLP immediately after the buffer becomes available (i.e. flags indicate the buffer is empty) then the data gets lost? And if you wait a bit more and then generate ZLP, then the transfer succeeds? BTW, how much do you wait? So, according your tests, there is significant difference whether you write data into buffer or generate ZLP there? Data can be written immediatly, ZLP not? How the read operation finishes in Host? Does it return with SUCCESS code, just with less data than expected? kalev |
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卡列夫
与1024字节写入（从FIFO到PC）的倍数有关的全缓冲测试的细节。 如果我检测到最后一个写在任何1024字节边界上，那么在写入最后4字节字（我有一个32位接口）时，我不设置PKKIT位。然后，我等待4个时钟周期，以确保标志已被更新。然后我检查并等待标志，表示设备已准备就绪。然后我开始发送ZLP。 对于小于或大于整个缓冲区大小（16384字节）的精确倍数的大小，这是有效的，并且PC接收正确的数据。 对于完全缓冲区大小（16384字节）的精确倍数，除了65536字节外，从FIFO接口对所有其他情况都起作用，除了PC没有任何响应（没有数据接收，没有任何数据丢失的指示，没有错误或问题），然后发送短数据包到PC和只有短的数据包是由PC接收的，所有的工作都很好。 注：我发现延迟并不总是有效的。 斯科特 以上来自于百度翻译 以下为原文 Kalev Specifics for full buffer test related to multiples of 1024 byte writes (slave FIFO to PC). If I detect a last write that falls on any 1024 byte boundary, I don't set the PKTEND bit when writing the last 4-byte word (I have a 32 bit interface). I then wait 4 clock cycles to ensure that the flag has been updated. Then I check and wait for the flag to indicates that the device is ready. I then proceed to send the ZLP. For sizes less than or more than the exact multiples of a full buffer size (16384 bytes), this works and the PC receives the data properly. For exact multiples of the full buffer size (16384 bytes), except at 65536 bytes, the slave FIFO interface acts as it does for all other cases, except there isn't any response from the PC (no data received, no indication of any lose of data, no errors or problems) I then send a short packet to the PC and only the short packet is received by the PC, with everything working just fine. Note: I have found out that the delay doesn't always work either. Scott |
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你好，
你使用哪个项目？您是使用AN694GPIF项目进行测试，还是您的项目？ 当做， 加亚特里 以上来自于百度翻译 以下为原文 Hi, which project ar eyou using? Are you testing using AN65974 GPIF project, or is that your custo project? Regards, Gayathri |
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嗨，史葛，探索GPIF和USB行为的想法很少。1）GPIF DMA状态机应向USB DMA自动提交满足的缓冲器。声明PKKADE应该强制GPIF提前提交下缓冲区。可以将DMA设置为手动模式，并仅用软件模拟数据发送。从软件提交完整的16384字节缓冲区和空0字节缓冲区应该相当于从GPIF发送16384字节。2）您可以注册DMA回调并验证那里，GPIF实际上提交给USB的缓冲区是什么。卡莱夫
以上来自于百度翻译 以下为原文 Hi Scott, Few ideas for exploring GPIF/USB behaviour. 1) GPIF DMA state machine should submit fulfilled buffers automatically to USB DMA. Asserting PKTEND should force GPIF to submit the underling buffer prematurely. You can set DMA to MANUAL mode and simulate data sending with software only. Committing full 16384 bytes buffer and empty 0 bytes buffer from software should be equivalent to how you send 16384 bytes from GPIF. 2) You can register DMA callbacks and verify there, what the buffers the GPIF actually submits to USB. br, kalev |
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您好，基于您的描述：
A）当您断言PKKADE时，如果缓冲区中有一些数据，一切都会正常工作。注意，根据缓冲区中的数据量，在这种情况下，FX3发送短数据包（数据不是1024倍）或ZLP（数据是1024倍）作为最后一个USB数据包。如果您已经切换到新的空缓冲区，声明PKTAN似乎会被忽略。但是，如果将数据写入此缓冲器，则以相同的时间执行标志的检查，数据是不可忽略的！我可以得出结论，FX3忽略了向主机发送空GPIF缓冲区的请求。但是你说，在坚持PKAdter之前等待一段时间是有帮助的。很奇怪。为什么这要取决于时机？你能用软件回调中的缓冲区做些什么吗？例如，丢弃空缓冲区？为了探索的目的，你也可以尝试只发送ZLPS根本没有数据。但总的来说，如果可能的话，我建议避免ZLPS，因为它们的“已知问题”。卡莱夫 以上来自于百度翻译 以下为原文 Hi, Based on your description: a) everything works if there is some data in a buffer when you assert PKTEND. Note that depending on amount of data in buffer, FX3 either sends a Short Packet (data is not 1024 multiple) or ZLP (data is 1024 multiple) as a last USB packet to host in this case. b) asserting PKTEND seems to be ignored if you have switched to new empty buffer. However, if you write data to this buffer, performing the check of flags exactly with same timings, data is not ignored! I could conclude that FX3 ignores the requests to send empty GPIF buffers to host. But you say that waiting a bit before asserting PKTEND mostly helps. Very strange. Why should this depend on timing? Could it be that you do something with buffers in software callbacks? For example discard empty buffers? For exploring purposes you could try also to send ZLPs only without data at all. But in general, if possible, I suggest to avoid ZLPs due to their "known issue". br, kalev |
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你好，
如果您使用的是从FIFO接口，那么断言包结束与最后一次写入。然后，FX3应该提交数据到主机。 当做， 隆皮 以上来自于百度翻译 以下为原文 Hi, if you are using the slave fifo interface then assert packet end with the last write. Then FX3 should commit the data to host. regards, lumpi |
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在上述情况下，当我发送1KB一次时，PC主机什么也没收到。
第二次发送后，PC接收到2个包，一个是2KB，另一个是0KB。 我不知道是什么原因。 以上来自于百度翻译 以下为原文 Under the situation mentioned above, pc host received nothing , when i send 1kB once. After the sending of the second time,PC received 2 packets, one is 2KB，another is 0KB. I don't know what 's the reasion. |
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