[问答]

I2C内核可以以任何速度运行还是只运行100KHz/400KHz？

问答对人有帮助，内容完整，我也想知道答案 0 I2C核心规范（）具有以下声明：该接口定义了3种传输速度： - 正常：100Kbps - 快速：400Kbps - 高速：3.5Mbps 直接支持仅100Kbps和400Kbps模式。适用于高速特殊IO 是必要的。如果这些IO可用并使用，则还支持高速。我们的设备最高速度为100KHz。我们认为最好以90KHz的频率运行器件，以避免在我们系统的整个工作温度范围内出现问题。当I2C总线未在其他器件上准备就绪时，我们遇到了问题。由于我们没有以100KHz运行，FPGA中的I2C模块是否有可能不稳定？以上来自于谷歌翻译以下为原文 The I2C core spec () has the following statement: The interface defines 3 transmission speeds: - Normal: 100Kbps - Fast: 400Kbps - High speed: 3.5Mbps Only 100Kbps and 400Kbps modes are supported directly. For High speed special IOs are needed. If these IOs are available and used, then High speed is also supported. We have a device that has a max speed of 100KHz. We thought it best to run the device at 90KHz to avoid problems over the entire operating temperature range of our system.We are have problems when the I2C bus is not coming ready on other devices. Is there any chance that the I2C module in the FPGA is not stable because we are not running at 100KHz? 0
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答案对人有帮助，有参考价值 0 billybob写道： I2C核心规范（）具有以下声明：该接口定义了3种传输速度： - 正常：100Kbps - 快速：400Kbps - 高速：3.5Mbps 直接支持仅100Kbps和400Kbps模式。适用于高速特殊IO 是必要的。如果这些IO可用并使用，则还支持高速。我们的设备最高速度为100KHz。我们认为最好以90KHz的频率运行器件，以避免在我们系统的整个工作温度范围内出现问题。当I2C总线未在其他器件上准备就绪时，我们遇到了问题。由于我们没有以100KHz运行，FPGA中的I2C模块是否有可能不稳定？ I2C将三种速度定义为“高达xxx kbits / s的比特率”，并阐明：“任何设备都可以以较低的总线速度运行。” 因此，没有理由不能以90 kbps的速率与标准模式（100 kbps）设备通信。话虽如此：谁写了你正在使用的I2C核心？时序参数或其他任何调整是否“知道”它是否在90 kHz工作？退一步：你确定I2C“核心”有什么好处吗？它是否经过模拟和验证？你确定你的硬件是否正确（适用于奴隶和主人等的VCC的适当上拉电阻等）？您确定您的设备地址是否正确并且您正在与存在的奴隶交谈？最后，我将说明我无法看到已经缓慢的100 kHz I2C总线减速10％会对工作温度范围产生任何可测量的影响。 ----------------------------是的，我这样做是为了谋生。以上来自于谷歌翻译以下为原文 billybob wrote: The I2C core spec () has the following statement: The interface defines 3 transmission speeds: - Normal: 100Kbps - Fast: 400Kbps - High speed: 3.5Mbps Only 100Kbps and 400Kbps modes are supported directly. For High speed special IOs are needed. If these IOs are available and used, then High speed is also supported. We have a device that has a max speed of 100KHz. We thought it best to run the device at 90KHz to avoid problems over the entire operating temperature range of our system.We are have problems when the I2C bus is not coming ready on other devices. Is there any chance that the I2C module in the FPGA is not stable because we are not running at 100KHz? The I2C defines the three speeds as "up to a bit rate of xxx kbits/s" and clarifies: "any device may be operated at a lower bus speed." So there's no reason why you can't talk to a Standard-mode (100 kbps) devices at 90 kbps. Having said that: who wrote the I2C core you're using? Are the timing parameters or whatever adjusted so that it "knows" it's working at 90 kHz? And stepping back a moment: are you sure the I2C "core" is any good? Has it been simulated and verified? Are you sure that your hardware is correct (proper pullup resistors for whatever VCC you use for the slaves and the master, etc etc)? Are you sure that your device addresses are correct and that you're talking to slaves that exist? And finally, I'll state that I can't see how slowing down the already-slow 100 kHz I2C bus by 10% will have any measurable impact on operating temperature range. ----------------------------Yes, I do this for a living.

2019-2-20 07:14:47 评论举报黄淳