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嗨，
我正在研究ISE 14.4中涉及Microblaze处理器的项目。 如果我的顶层模块是一个ISE项目，也请参与EDK，请指导我如何为这样的项目进行功能模拟。 谢谢。 以上来自于谷歌翻译 以下为原文 Hi, I am working on projects involving Microblaze processor in ISE 14.4. Please guide me on how to do a functional simulation for such a project if my top level module is an ISE project, with EDK also involved. Thanks. 
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27个回答
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检查此主题中的步骤：http：//forums.xilinx.com/t5/Embedded-Development-Tools/Microblaze-Simulation/m-p/385133#M29401
以上来自于谷歌翻译 以下为原文 check the steps in this thread: http://forums.xilinx.com/t5/Embedded-Development-Tools/Microblaze-Simulation/m-p/385133#M29401 |
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我刚检查了这个程序。
但是当我转到“项目选项”时，默认情况下会禁用我的一些选项，例如“将时序收敛失败视为错误”和“生成测试工作台模板”。 这是相同的快照 以上来自于谷歌翻译 以下为原文 I have just checked this procedure. But when I go to "Project Options", some of my options like "Treat timing closure failure as an error", and "Generate test bench template" are disabled by default. Here is a snapshot of the same |
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为什么？
另外，在您要求我引用的链接中，是否有任何剩余的步骤来完成功能模拟或者这些都是？ 谢谢。 问候， 苏里亚 以上来自于谷歌翻译 以下为原文 Why is that so? Also, in the link which you had asked me to refer, are there any remaining steps to complete the functional simulation or those are all? Thanks. Regards, Surya |
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如屏幕截图中的第一句显示，您应该从ISE执行模拟（因为这是您的顶级位置）。
在Hierarchy窗口中选择您的顶级模块，然后选择Simulation选项卡并从那里运行sim。如果您还没有，那么您可能需要一个像样的测试平台。 您是否打算在模拟过程中在Microblaze上执行代码？如果是这样，您应该确保.ELF包含在模拟文件中。 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 As the first sentence in your screenshot shows, you should execute the simulation from ISE (as that is where your top level is). Select your top level module in the Hierarchy window, then choose the Simulation tab and run the sim from there. If you don't have one already, you'll probably need a decent testbench. Is your intention to execute code on the Microblaze during simulation? If so, you should make sure that the .ELF is included in the simulation files. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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如果XPS是您的ISE设计中的子系统，您将需要如前所述从ISE进行模拟。如果您准备好了精灵并且与模拟源相关联，那么您就可以开始了。
以上来自于谷歌翻译 以下为原文 If the XPS is a sub-system within your ISE design, you will need to simulate from ISE as previously mentioned. If you have your elf ready and have associated with your simulation sources then you are good to go. |
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我的项目现在只包含一个微光泽处理器和一些外围设备，如LED，DIP开关等。我试图模拟一个应用程序，它基本上以某种频率切换LED。
是的，我的意思是在模拟过程中在Microblaze上执行代码。 那么我需要遵循哪些步骤？ 谢谢 以上来自于谷歌翻译 以下为原文 My project now contains only a microblaze processor and some peripherals like LEDs, DIP Switches etc. I was trying to simulate a application, which basically toggles the LEDs at some frequency. Yes, my intention is to execute code on the Microblaze during simulation. What are the steps I need to follow then? Thanks |
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按照上述步骤操作。
如果您有任何错误，请告诉我们。谢谢 -------------------------------------------------- -----------------------不要忘记回答，kudo，并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Follow the above mentioned steps. If you any error then let us know. Thanks------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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查看附件。
这是PA / XPS流程，但ISE / XPS不应该有太大的不同。 AXI_DDR3_SIM_PA.pdf 326 KB 以上来自于谷歌翻译 以下为原文 Check the attached doc. It is PA/XPS flow but ISE/XPS should not be much different. |
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感谢您查看我的问题。
如果有任何错误，我会按照步骤告知您。 以上来自于谷歌翻译 以下为原文 Thanks for looking into my issue. I will follow the steps and let you know in case of any errors. |
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我已按照附件中给出的步骤操作，并将其应用于ISE。
我在SDK中编写的应用程序切换LED。 在模拟时，我的Isim窗口打开，但我没有在LED上获得任何输出。 在ISim窗口中唯一变化的信号是clk_p和clk_n，而leds_8bits_tri_o [7：0]始终保持为0。 另外，如果我运行模拟一段时间，那么唯一改变的信号就是clk_p和clk_n。 哪里可能出错？ 谢谢。 以上来自于谷歌翻译 以下为原文 I have followed the steps given in the attachment, and applied the same to ISE. The application I have written in the SDK toggles the LEDs. On simulation, my Isim Window opens, but I am not getting any output on the LEDs. The only signals which are changing in the ISim window are clk_p and clk_n, while the leds_8bits_tri_o[7:0] remains 0 all the time. Also, if I run my simulation for a longer time, the only signals which change are, again, clk_p and clk_n. Where could I be possibly going wrong? Thanks. |
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您应该附加测试平台和一些波形。
系统是否仍处于重置状态？ 你实际运行模拟多长时间了？ DCM（如果有的话）是否已锁定？ ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 You should attach your testbench and some waveforms. Is the system still in reset? How long are you actually running the simulation for? Is the DCM (if you have one) locked? ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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我的测试台没有任何刺激。
但是，由于我的SDK应用程序切换LED并且因为我已将.ELF文件附加到测试平台中，即使我没有给出任何刺激，我的波形是否应该指示LED的切换？ 我在5ns和10ns时附加了波形。 在5ns- 在10ns- 我还附上了测试台。 谢谢 Testbench.vhd 4 KB 以上来自于谷歌翻译 以下为原文 My testbench doesn't have any stimulus. But since my SDK application toggles the LEDs and since I have attached the .ELF file in the testbench, even though i dont give any stimulus, shouldn't my waveform indicate the toggling of LEDs? I have attached the waveforms at time 5ns and 10ns. At 5ns- At 10ns- I have also attached the testbench. Thanks |
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您的测试台不会对RESET信号执行任何操作。
它是高有效还是低有效？它始终很低。 当某个地方存在活动的复位边缘（或电平）变化时，系统通常会更好地工作。 您的时钟周期为10 ns。 您的两个屏幕截图达到10 ns。 您在1个单一时钟周期内预计会有多少活动？ 为什么差分时钟信号具有相同的值，即它们在同一时间为0和1。 差分信号不起作用。 模拟可能包括嵌入在FPGA中的GSR（全局系统复位）。 这将需要一些时间，可能需要超过10 ns才能完成。 10 ns是NOWHERE接近足够的时间允许系统时钟的DCM锁定并提供可用的输出，处理器复位模块（我假设您的嵌入式系统中有一个？）也可以释放处理器和总线复位。 简而言之，修复差分时钟，正确运行RESET线并确保模拟运行几毫秒（如果您想观察LED驱动信号切换，可能需要数百毫秒）。 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 Your testbench does nothing with the RESET signal. Is it active high or active low? It is always low. Systems often work better when there is an active reset edge (or level) change, somewhere. Your clock period is 10 ns. Your two screenshots amount to 10 ns. How much activity are you expecting in 1 single clock period? Why do your DIFFERENTIAL clock signals have the same values, i.e. they are 0 and 1 AT THE SAME TIME. Differential signals don't work like that. The simulation may well be including the GSR (Global System Reset) that is embedded in the FPGA. This will take some time and probably longer than 10 ns to complete. 10 ns is NOWHERE near enough time to allow the system clock's DCM to lock and provide a usable output, nor for the processor reset module (I assume you have one in your embedded system?) to release the processor and bus resets. In short, fix your differential clock, exercise the RESET line correctly and ensure that your simulation runs for several ms (hundreds, probably, if you want to observe LED drive signals toggling). ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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我没有使用任何DCM。
我已经向您展示了仅5ns和10ns的波形，而我的实际模拟运行的时间远远多于此（考虑到LED切换所需的时间）。 由于波形每5ns不断变化，我只是连接了前2个波形。 此外，我将更改差分信号，并包括RESET并让您知道会发生什么。 谢谢， 苏里亚 以上来自于谷歌翻译 以下为原文 I am not using any DCM. I have shown you the waveforms at only 5ns and 10ns, while my actual simulation runs a lot more time than that(keeping in consideration the time taken for LEDs to toggle). Since, the waveforms keep changing every 5ns, I just attached the first 2 ones. Also, I will change the differential signals, and include RESET and let you know what happens. Thanks, Surya |
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我改变了差分时钟，在引入RESET后，我的模拟运行了。
但由于一些奇怪的原因，LED输出为11110000，与SDK应用无关。 我已将波形和测试平台连接在下面。 Testbench.vhd 4 KB 以上来自于谷歌翻译 以下为原文 I have changed the differential clock and after introducing RESET, my simulation runs. But for some strange reason, LEDs output is 11110000, irrespective of SDK application. I have attached the waveform and the testbench below. |
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我的SDK应用程序使得LED_8bits的前4位每5us切换一次，即o / p应为11110000,00001111,1111000000,00001111等等。
谢谢， 苏里亚 以上来自于谷歌翻译 以下为原文 My SDK application is such that the first 4 bits of LED_8bits toggle every 5us, i.e., the o/p should be 11110000, 00001111, 11110000, 00001111, and so on.. Thanks, Surya |
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您说输出与应用程序无关，那么您如何知道Microblaze正在执行代码？
您可以在模拟过程中查看嵌入式系统并查看Microblaze或内部总线上的活动吗？ 如果无法看到嵌入式系统的定义，我只能猜测。 也许你可以附上你的MHS。 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 You say that the output is irrespective of the application so how do you know that the Microblaze is executing the code? Can you look at the embedded system during your simulation and see activity on the Microblaze or internal busses? Without being able to see the definition of your embedded system, I can only guess. May be you can attach your MHS. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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None
以上来自于谷歌翻译 以下为原文 Like you said, I was looking into the internal signals and then I came across the trigger object, and since LEDs are outputs, all the 8 bits of trigger must be 0. So, I guessed thats why my output wasn't changing and remaining 11110000 all the time. So I changed the same in the SDK, but still it won't change (as shown in the attached waveform). I am also attaching the MHS file. Kindly look into the same. Thanks. |
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我不确定你的“触发对象”是什么意思。
你的意思是GPIO对LED有三态吗？ 我在你的MHS中看不到任何不幸的事情。 正如我在之前的消息中暗示的那样，您应该查看时钟发生器模块的时钟输出（我写了DCM，但我的意思是任何时钟管理模块）。 我看到您的测试平台为差分时钟设置了10 ns周期（100 MHz），但您的时钟发生器需要5 ns（200 MHz）输入。 为什么在测试平台中使用不同的时钟周期？ 我仍然期望时钟发生器的一些锁定时钟输出，但我在你的截图中看不到它。 您需要在模拟中确认处理器实际上正在尝试执行某些操作。 你能看到公共汽车活动吗？ 你能看到时钟发生器输出吗？ 你能看到AXI互连从复位中释放出来吗？ 您的顶级信号的屏幕截图对于更深层次的问题并没有任何用处。 ----------“我们必须学会做的事情，我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 I'm not sure what you mean by "trigger object". Do you mean the GPIO tristate on for the LEDs? I can't see anything untoward in your MHS. As I implied in an earlier message, you should look at the clock outputs of the clock generator module (I wrote DCM but I meant ANY clock management block). I see that your testbench sets up a 10 ns period (100 MHz) for your differential clock but your clock generator is expecting a 5 ns (200 MHz) input. Why are you using a different clock period in your testbench? I would still have expected some locked clock output from the clock generator but I can't see it in your screenshots. You NEED to confirm, in your simulation, that the processor is actually trying to do something. Can you see bus activity? Can you see the clock generator output? Can you see that the AXI interconnect is released from reset? Screenshots of your top level signals aren't really of any use for deeper issues. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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