请问TVP7002怎么输出BT1120 YCbCr 4:2:2?

Hi Ocean，
Please check attached excel to find the setting of "TVP7002 - VGA to YCbCr 422 DS"

Hi Nick Dai i had check it but also found nothing about csc coeficient setting from Reg 0x4A to 0x5B,which can support BT.1120 output.

Hi Ocean，
Below setting may help you.
* INPUT of TVP7002 -> YPbPr (component) 1080p 60fps
* OUTPUT of TVP7002 -> 20-bit 4:2:2 YCbCr with Embedded Sync
BEGIN_DATASET

DATASET_NAME,"1080p60, 60Hz, 67.5kHz, 148.5MHz, YPbPr>YCbCr 422 ES"

//TVP7002
//INCLUDE,TVP7002_default_settings.inc // default values to be used unless later modified
WR_REG,TVP7000,0x01,0x01,0x67 // H-PLL FEEDBACK DIVIDER MSB
WR_REG,TVP7000,0x01,0x02,0x20 // H-PLL FEEDBACK DIVIDER LSB
WR_REG,TVP7000,0x01,0x03,0xA8 // H-PLL CONTROL
WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL PHASE SELECT
WR_REG,TVP7000,0x01,0x05,0x32 // CLAMP START
WR_REG,TVP7000,0x01,0x06,0x20 // CLAMP WIDTH
WR_REG,TVP7000,0x01,0x07,0x20 // HSOUT OUTPUT WIDTH
WR_REG,TVP7000,0x01,0x08,0x00 // BLU FINE GAIN
WR_REG,TVP7000,0x01,0x09,0x00 // GRN FINE GAIN
WR_REG,TVP7000,0x01,0x0A,0x00 // RED FINE GAIN
WR_REG,TVP7000,0x01,0x0B,0x80 // BLU FINE OFFSET
WR_REG,TVP7000,0x01,0x0C,0x80 // GRN FINE OFFSET
WR_REG,TVP7000,0x01,0x0D,0x80 // RED FINE OFFSET
WR_REG,TVP7000,0x01,0x0E,0x5B // SYNC CONTROL 1
WR_REG,TVP7000,0x01,0x0F,0x2A // H-PLL AND CLAMP CONTROL
WR_REG,TVP7000,0x01,0x10,0x5D // SYNC ON GREEN THRESHOLD
WR_REG,TVP7000,0x01,0x11,0x20 // SYNC SEPERATOR THRESHOLD
WR_REG,TVP7000,0x01,0x12,0x00 // H-PLL PRE-COAST
WR_REG,TVP7000,0x01,0x13,0x00 // H-PLL POST-COAST
WR_REG,TVP7000,0x01,0x15,0x04 // OUTPUT FORMATTER
WR_REG,TVP7000,0x01,0x16,0x11 // MISC CONTROL 1
WR_REG,TVP7000,0x01,0x17,0x03 // MISC CONTROL 2
WR_REG,TVP7000,0x01,0x18,0x00 // MISC CONTROL 3
WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT 1
WR_REG,TVP7000,0x01,0x1A,0xC2 // INPUT MUX SELECT 2
WR_REG,TVP7000,0x01,0x1B,0x77 // BLU AND GRN COARSE GAIN
WR_REG,TVP7000,0x01,0x1C,0x07 // RED COARSE GAIN
WR_REG,TVP7000,0x01,0x1D,0x00 // FINE OFFSET LSB
WR_REG,TVP7000,0x01,0x1E,0x10 // BLU COARSE OFFSET
WR_REG,TVP7000,0x01,0x1F,0x10 // GRN COARSE OFFSET
WR_REG,TVP7000,0x01,0x20,0x10 // RED COARSE OFFSET
WR_REG,TVP7000,0x01,0x21,0x0D // HSOUT OUTPUT START
WR_REG,TVP7000,0x01,0x22,0x08 // MISC CONTROL 4
WR_REG,TVP7000,0x01,0x26,0x80 // AUTO LEVEL CONTROL ENABLE
WR_REG,TVP7000,0x01,0x28,0x53 // AUTO LEVEL CONTROL FILTER
WR_REG,TVP7000,0x01,0x29,0x08 // ADC TEST CONTROL
WR_REG,TVP7000,0x01,0x2A,0x03 // FINE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL
WR_REG,TVP7000,0x01,0x2C,0x50 // ADC SETUP
WR_REG,TVP7000,0x01,0x2D,0x00 // COARSE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x2E,0x80 // SOG CLAMP CONTROL
WR_REG,TVP7000,0x01,0x2F,0x0C // RGB COARSE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x30,0x04 // SOG COARSE CLAMP CONTROL
WR_REG,TVP7000,0x01,0x31,0x5A // AUTO LEVEL CONTROL PLACEMENT
WR_REG,TVP7000,0x01,0x34,0x03 // MACROVISION STRIPPER WIDTH
WR_REG,TVP7000,0x01,0x35,0x10 // VSYNC ALIGNMENT
WR_REG,TVP7000,0x01,0x36,0x00 // SYNC BYPASS
WR_REG,TVP7000,0x01,0x3D,0x03 // LINE LENGTH TOLERANCE
WR_REG,TVP7000,0x01,0x3F,0x00 // VIDEO BANDWIDTH CONTROL
WR_REG,TVP7000,0x01,0x40,0x2C // AVID START PIXEL LSB
WR_REG,TVP7000,0x01,0x41,0x01 // AVID START PIXEL MSB
WR_REG,TVP7000,0x01,0x42,0x2C // AVID STOP PIXEL LSB
WR_REG,TVP7000,0x01,0x43,0x06 // AVID STOP PIXEL MSB
WR_REG,TVP7000,0x01,0x44,0x05 // VBLK START LINE OFFSET (F0)
WR_REG,TVP7000,0x01,0x45,0x05 // VBLK START LINE OFFSET (F1)
WR_REG,TVP7000,0x01,0x46,0x1E // VBLK DURATION (F0)
WR_REG,TVP7000,0x01,0x47,0x1E // VBLK DURATION (F1)
WR_REG,TVP7000,0x01,0x48,0x00 // F-BIT START LINE OFFSET (F0)
WR_REG,TVP7000,0x01,0x49,0x00 // F-BIT START LINE OFFSET (F1)
WR_REG,TVP7000,0x01,0x4A,0xE3 // 1ST CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x4B,0x16 // 1ST CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x4C,0x4F // 2ND CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x4D,0x02 // 2ND CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x4E,0xCE // 3RD CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x4F,0x06 // 3RD CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x50,0xAB // 4TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x51,0xF3 // 4TH CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x52,0x00 // 5TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x53,0x10 // 5TH CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x54,0x55 // 6TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x55,0xFC // 6TH CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x56,0x78 // 7TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x57,0xF1 // 7TH CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x58,0x88 // 8TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x59,0xFE // 8TH CSC COEFFICIENT MSB
WR_REG,TVP7000,0x01,0x5A,0x00 // 9TH CSC COEFFICIENT LSB
WR_REG,TVP7000,0x01,0x5B,0x10 // 9TH CSC COEFFICIENT MSB



//INCLUDE,TVP7002_YPbPr_to_YCbCr_422_ES_common.inc
////////////////////////////////////////////////////////////////////////////////
// Include File: TVP7002_YPbPr_to_YCbCr_422_ES_common.inc
// Release Date: 10-26-2011
// For use with the TVP7002+THS8200 EVM Kit
// Common TVP7002 control register settings for
// - Input: SD/EDTV YPbPr (bi-level sync) and HDTV YPbPr (tri-level sync)
// - Output: 20-bit YCbCr 4:2:2 with embedded syncs and discrete syncs
// Some fine gain adjustment may be required (see registers 0x08, 0x09 and 0x0A)
////////////////////////////////////////////////////////////////////////////////

// Common register settings for YPbPr input
WR_REG,TVP7000,0x01,0x0F,0x2E // H-PLL and Clamp Control (default)
WR_REG,TVP7000,0x01,0x10,0x5D // Sync On Green Threshold (default), YPbPr clamp
WR_REG,TVP7000,0x01,0x11,0x40 // Sync Separator Threshold
WR_REG,TVP7000,0x01,0x19,0x00 // Input Mux Select 1, CH1 selected (BNC inputs)
WR_REG,TVP7000,0x01,0x26,0x80 // ALC Enable (default)
WR_REG,TVP7000,0x01,0x28,0x53 // ALC Filter (default)
WR_REG,TVP7000,0x01,0x2A,0x87 // Fine Clamp Control, CM offset enabled, fine clamp enabled
WR_REG,TVP7000,0x01,0x2B,0x00 // Power Control (default), SOG ON
WR_REG,TVP7000,0x01,0x2D,0x00 // Coarse Clamp Control (default), coarse clamp disabled
WR_REG,TVP7000,0x01,0x2E,0x80 // SOG Clamp (default), SOG clamp enabled
WR_REG,TVP7000,0x01,0x35,0x00 // VSYNC Alignment
WR_REG,TVP7000,0x01,0x36,0x00 // Sync Bypass (default)
WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)

// Common register settings for 20-bit YCbCr 4:2:2 output
WR_REG,TVP7000,0x01,0x08,0x04 // Blue Fine Gain (default), normal CbCr alignment
WR_REG,TVP7000,0x01,0x09,0x04 // Green Fine Gain (default) = 256*((876/1024)*1000mV/700mV/1.2 - 1)
WR_REG,TVP7000,0x01,0x0A,0x04 // Red Fine Gain (default)
WR_REG,TVP7000,0x01,0x0B,0x90 // Blue Fine Offset MSBs
WR_REG,TVP7000,0x01,0x0C,0x90 // Green Fine Offset MSBs
WR_REG,TVP7000,0x01,0x0D,0x90 // Red Fine Offset MSBs
WR_REG,TVP7000,0x01,0x15,0x47 // Output Formatter, BT.601 coding range, CrCb order, 20-bit 4:2:2 output, embedded syncs enabled
WR_REG,TVP7000,0x01,0x16,0x01 // MISC Control 1 (default), alternate CbCr alignment???
WR_REG,TVP7000,0x01,0x17,0x00 // MISC Control 2, FID output, outputs enabled
WR_REG,TVP7000,0x01,0x18,0x01 // MISC Control 3, CSC disabled, normal FID polarity, data clocked out on falling edge



//Specific mode settings
WR_REG,TVP7000,0x01,0x01,0x89 // H-PLL Feedback Divider MSBs 2200
WR_REG,TVP7000,0x01,0x02,0x80 // H-PLL Feedback Divider LSBs
WR_REG,TVP7000,0x01,0x03,0xE0 // H-PLL Control
WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL Phase Select, CKDI, CKDI, DIV2
WR_REG,TVP7000,0x01,0x05,0x32 // Clamp Start
WR_REG,TVP7000,0x01,0x06,0x20 // Clamp Width
WR_REG,TVP7000,0x01,0x07,0x2C // HSYNC Output Width - 44
WR_REG,TVP7000,0x01,0x0E,0x3F // Sync Control 1 HSout+
WR_REG,TVP7000,0x01,0x12,0x00 // H-PLL Pre-Coast
WR_REG,TVP7000,0x01,0x13,0x01 // H-PLL Post-Coast
WR_REG,TVP7000,0x01,0x1A,0xCF // Input Mux Select 2, SOG LPF bypassed, 4.8MHz CLP LPF, EXT REFCLK, HSYNC_B and VSYNC_B selected
WR_REG,TVP7000,0x01,0x21,0x35 // HSOUT Output Start
WR_REG,TVP7000,0x01,0x22,0x00 // MISC Control 4 - Macrovision stripper disabled
WR_REG,TVP7000,0x01,0x2C,0x80 // ADC Setup
WR_REG,TVP7000,0x01,0x31,0x5A // ALC Placement
//REG34h only required if MACEN bit is set in REG22h
//WR_REG,TVP7000,0x01,0x34,0x03 // Macrovision Stripper Width when internal REFCLK is used
WR_REG,TVP7000,0x01,0x34,0x09 // Macrovision Stripper Width when 27MHz EXT REFCLK is used
WR_REG,TVP7000,0x01,0x3F,0x00 // Video Bandwidth Control, maximum B/W selected
//embedded syncs
WR_REG,TVP7000,0x01,0x40,0x07 // AVID Start Pixel LSB 263 (236 + 27) for SOG filter difference
WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start Pixel LSB
WR_REG,TVP7000,0x01,0x42,0x8B // AVID Stop Pixel LSB 2187 (AVID Start + 1920 + 4)
WR_REG,TVP7000,0x01,0x43,0x08 // AVID Stop Pixel LSB
WR_REG,TVP7000,0x01,0x44,0x04 // VBLK F0 Start Line Offset
WR_REG,TVP7000,0x01,0x45,0x04 // VBLK F1 Start Line Offset
WR_REG,TVP7000,0x01,0x46,0x2D // VBLK F0 Duration
WR_REG,TVP7000,0x01,0x47,0x2D // VBLK F1 Duration
WR_REG,TVP7000,0x01,0x48,0x00 // F-bit F0 Start Line Offset (default)
WR_REG,TVP7000,0x01,0x49,0x00 // F-bit F1 Start Line Offset (default)

你好，我的输入信号是 VESA 标准的 5-wire PC VGA （1280x720@60）信号,。我需要输出 BT709的 YCbCr 4:2:2信号，按照附件的参数设置了寄存器
我用示波器检查了输出结果，它的H,V，Pixel frequence 都和我需要的一致，但是DE（data enable ）高达40KHz,远远大于我需要的输出结果（30Hz）,请问应该配置哪些寄存器？

DE( data enable)你指的TVP7002的FIDOUT这个引脚吗？

是的，pin22

I want to change the Image resolution(1280x1024),What need to change?

你的意思是使用TVP7002 VGA(1280x1024) to YCbCr 422 BT.1120输出的寄存器配置？如果是的话，二楼提供的Excel表格里也有。

ok,thanks!

http://www.deyisupport.com/question_answer/dsp_arm/davinci_digital_media_processors/f/39/t/52747.aspx
你可以到我以前的帖子里面找到寄存器配置表

我现在按照表格中的数据配置后，图像有两个问题。首先，在屏幕的上方有黑边，其次是图像会发生错位（在视频源端图像在中间位置，在目标端上显示的画面垂直向上移动一些），请问下怎么会导致这种现象？有什么解决的方法？谢谢！

我记得是有一些什么start line之类的寄存器调一下就行了。

请问TVP7002输出是隔行还是逐行，另外麻烦提供一下供应商联系方式，需要相关资料，谢谢！