哪个报告包含有关设计中时钟数的准确信息？

如果您使用ISE，最好和最准确的是在PAR之后检查。
您可以通过查看布局布线报告中的“时钟报告”部分来验证所有时钟是否正在使用正确的时钟布线资源。
例如，检查报告以确保不使用本地路由资源路由时钟。
“时钟报告”部分列出了以下内容：
由布局布线过程检测到的时钟网络
时钟网路由的时钟缓冲资源
时钟扇出
净倾斜
时钟网络到时钟负载的最大延迟
在vivado的情况下，有一些特定的tcl命令可用于获得时钟交互，时钟利用等。



以下为原文

The best and most accurate would be to check after PAR if you are using ISE.

You can verify that all of your clocks are using the proper clock routing resources by reviewing the “Clock Report” section in the Place and Route Report. For example, check the report to ensure that clocks were not routed using local routing resources. The “Clock Report” section lists the following:

• Clock nets detected by the Place and Route process
  
• Clock buffer resources that clock nets are routed through
  
• Clock fanout
  
• Net skew
  
• Maximum delay of the clock net to the clock loads
  

In case of vivado, there are specific tcl commands that you could use to get clock intercation, clock utililization,etc.

嗨Vintu，
您的查询是否已解决？
如果已解决，请将解决方案标记为答案。
如果还没有解决，请进一步说明。
甚至综合报告也应该显示时钟。
你能告诉我RTL原理图中只有你在综合报告中看不到的时钟信号吗？
同时复制粘贴综合报告中生成的时钟报告和本文中的PAR报告，以便我们进一步帮助您。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi Vintu,

Is your query resolved? In case it is resolved, please mark the solution as an answer.

Further notes in case it is not yet resolved.

Even the synthesis report should be showing the clocks. Can you show me in the RTL schematic, only the clock signal which you cannot see in the synthesis report.

Also copy paste your clock report generated in Synthesis report and the PAR report in this post so that we can further help you out.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.