层次结构设计是否意味着将一个大模块分成几个子模块？

嗨佛，
你是指偶然提到“等级设计”吗？
那么对于真正的大型FPGA，假设项目从一开始就开始，你真的想要遵循这种方法。
无论如何，您的设计必须始终具有结构良好的层次结构。
在我看来，会有一些不同意的人，分层设计只对真正的大型FPGA有利。
实际上，即使是中等密度的7系列FPGA也不会从中受益。
我们尝试过，我们说我们现在的项目不会遵循这一点。
在一个非常一般的上下文中做出这个评论，明显的，也许是唯一的专业人员（但是一个大专业人员！）是分层设计将缩短迭代运行时间，因为你将仅合成/放置/路由层次结构的一部分（这里
：模块）的设计而不是整个设计。
这种方法有一些缺点，它们将在以下方面更加明显：
a）高速宽总线设计恕我直言是一个不分层次的设计。
这与该工具几乎没有任何关系。
b）预期资源使用率约为50％或更高的FPGA。
c）你需要确保你遵循这些“分区”的严格指导原则，所以为了举例，如果你正在接管别人的设计，那么通过“分层设计”把它作为一个坏主意：o）
d）所有设计检查点，位文件生成，STA等的聚合将加起来，因此必须始终评估设置真正的分层设计流程是否真的值得花时间。
FPGA越大，“值得”做的就越多。
详细说明b），您通常会为特定模块分配芯片的RECTANGLE区域作为您的区域约束（在ISE中也称为“分区”），因此一旦分配了该区域，就无法在该区域中添加任何逻辑。
因此，您的有效FPGA逻辑使用率会降低。
此外，该工具尚未真正“人口统计学意识到”，即它不知道特定的FF或总线是否应该到达矩形分区的顶部/底部/左侧/右侧。
BR
弗拉德
弗拉迪斯拉夫·穆拉文
在原帖中查看解决方案



以下为原文

Hi Buddha,

Are you referring to "hierarchial design" by chance? Then for REALLY large FPGAs, you would really want to follow this approach assuming the project starts at the beginning. And regardless, your design must always have a well-structured hierarchy.

In my opinion, and there will be a number of those who disagree, the hierarchical design is ONLY good for REALLY large FPGAs. In fact, even the medium-density 7-series FPGAs will not benefit from it. We tried and we said we'll not follow that for our current project.

Making this comment in a very general context, the obvious and perhaps the only pro (but a big pro!) is that the hierarchical design will shorten an iteration runtime since you will be synthesizing/placing/routing only the part of the hierarchy (here: module) of the design and not the entire design.

There are some cons for this approach, and they will be more visible in:
a) High-speed wide-bus design IMHO is a no-go with hierarchical design. This has little or nothing to do with the tool.
b) an FPGA with anticipated resource usage of approximately 50% or higher.
c) You need to make sure you are following strict guidelines for these "partitions", so for the sake of example, if you are taking over someone else's design, it is a bad idea to put it thru "hierarchical design" :o)
d) The aggregation of the all design checkpoints, the bitfile generation, the STA etc will add up, so one must always evaluate whether setting up a truly hierarchical design flow really worth spending time for. The larger FPGA is, the more it will be "worth" doing.

Elaborating on b), you would normally allocate a RECTANGLE area of the chip for a particular module to be your area constraint (aka "partition" in ISE), so once you allocated this area, you cannot put any more logic in that area. Therefore, your effective FPGA logic usage decreases. Furthermore, the tool is not really "demographically aware" yet, i.e. it would not know whether a particular FF or a bus should go to the top/bottom/left/right of the rectangle partition.

BR
Vlad
Vladislav MuravinView solution in original post

嗨佛，
你是指偶然提到“等级设计”吗？
那么对于真正的大型FPGA，假设项目从一开始就开始，你真的想要遵循这种方法。
无论如何，您的设计必须始终具有结构良好的层次结构。
在我看来，会有一些不同意的人，分层设计只对真正的大型FPGA有利。
实际上，即使是中等密度的7系列FPGA也不会从中受益。
我们尝试过，我们说我们现在的项目不会遵循这一点。
在一个非常一般的上下文中做出这个评论，明显的，也许是唯一的专业人员（但是一个大专业人员！）是分层设计将缩短迭代运行时间，因为你将仅合成/放置/路由层次结构的一部分（这里
：模块）的设计而不是整个设计。
这种方法有一些缺点，它们将在以下方面更加明显：
a）高速宽总线设计恕我直言是一个不分层次的设计。
这与该工具几乎没有任何关系。
b）预期资源使用率约为50％或更高的FPGA。
c）你需要确保你遵循这些“分区”的严格指导原则，所以为了举例，如果你正在接管别人的设计，那么通过“分层设计”把它作为一个坏主意：o）
d）所有设计检查点，位文件生成，STA等的聚合将加起来，因此必须始终评估设置真正的分层设计流程是否真的值得花时间。
FPGA越大，“值得”做的就越多。
详细说明b），您通常会为特定模块分配芯片的RECTANGLE区域作为您的区域约束（在ISE中也称为“分区”），因此一旦分配了该区域，就无法在该区域中添加任何逻辑。
因此，您的有效FPGA逻辑使用率会降低。
此外，该工具尚未真正“人口统计学意识到”，即它不知道特定的FF或总线是否应该到达矩形分区的顶部/底部/左侧/右侧。
BR
弗拉德
弗拉迪斯拉夫·穆拉文



以下为原文

Hi Buddha,

Are you referring to "hierarchial design" by chance? Then for REALLY large FPGAs, you would really want to follow this approach assuming the project starts at the beginning. And regardless, your design must always have a well-structured hierarchy.

In my opinion, and there will be a number of those who disagree, the hierarchical design is ONLY good for REALLY large FPGAs. In fact, even the medium-density 7-series FPGAs will not benefit from it. We tried and we said we'll not follow that for our current project.

Making this comment in a very general context, the obvious and perhaps the only pro (but a big pro!) is that the hierarchical design will shorten an iteration runtime since you will be synthesizing/placing/routing only the part of the hierarchy (here: module) of the design and not the entire design.

There are some cons for this approach, and they will be more visible in:
a) High-speed wide-bus design IMHO is a no-go with hierarchical design. This has little or nothing to do with the tool.
b) an FPGA with anticipated resource usage of approximately 50% or higher.
c) You need to make sure you are following strict guidelines for these "partitions", so for the sake of example, if you are taking over someone else's design, it is a bad idea to put it thru "hierarchical design" :o)
d) The aggregation of the all design checkpoints, the bitfile generation, the STA etc will add up, so one must always evaluate whether setting up a truly hierarchical design flow really worth spending time for. The larger FPGA is, the more it will be "worth" doing.

Elaborating on b), you would normally allocate a RECTANGLE area of the chip for a particular module to be your area constraint (aka "partition" in ISE), so once you allocated this area, you cannot put any more logic in that area. Therefore, your effective FPGA logic usage decreases. Furthermore, the tool is not really "demographically aware" yet, i.e. it would not know whether a particular FF or a bus should go to the top/bottom/left/right of the rectangle partition.

BR
Vlad
Vladislav Muravin

嗨Vald，非常感谢您的回复。
所以一般来说，我提到的“将一个大模块分成几个子模块而不是在一个HDL文件中创建一个大模块”的想法不是分层设计。
这只是正常的设计，对吧？我试着找到Xilinx文档，对层次设计有一个基本的了解。
我只找到UG748：分层设计方法指南。
但它有点过时，写于4月210日2103。您认为这是正确的文件吗？



以下为原文

Hi Vald,

Thanks very much for reply. So generally speaking, the idea I mentioned "seperate a big module into several submodule instead of make a big module in one HDL file" is not hierarchial design. It is just normal design, right?

I try to find the Xilinx document to have a basic understanding about hierarchial design. I only find UG748 : Hierarchical Design Methodology Guide. But it is a little out of date which was written in 2103 Apr 10. Do you think this is the right document to read?

是的，无论您选择哪个部分，拥有良好的层次结构设计总是好的。
至于文档，你想阅读ug904 / 5。
弗拉迪斯拉夫·穆拉文



以下为原文

Yes, regardless of which part you choose, it is always good to have a good hierarchy-structured designh. As for the docs, you want to read ug904/5.

Vladislav Muravin

谢谢Vald。



以下为原文

Thanks Vald.