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我们尝试使用SPI和RTC在自动存储模式下使用CY14B101P存储器。在表1中的第3页的产品数据表引脚定义CS引脚在被拉低时激活设备(GND)?还是没有连接??)但是在第5页(OF34)的图N.2自动存储模式下,CS被用10K电阻拉到VCC上(当电源接通时总是拔起)。!!!)在另一个产品类似的数据表(NRTRAM与RTC,但不是没有SPI接口)CY14B101KA在第4页上有相同的卓尔(图2自动存储模式),但这thime我们被拉上WCC与10 K电阻,这证明是真正的配置!在另一个柏树文档中,第1页上的应用注意事项AN43596,卓尔图形1报告了一个自动存储配置,然后等于CY14B101KA数据表。另一个问题:我们使用单芯片模式:保持引脚被拉上的VCC或GND的工作????请把错误告诉我!我们失去了很多时间来重新设计我们的项目!!!!
以上来自于百度翻译 以下为原文 we try to use CY14B101P memory with SPI and RTC in AUTOSTORE MODE. on product datasheet at page 3 in table 1 Pin definition the CS pin active the device when is pulled low (GND?? or not connected??). BUT at page 5(of34) on FIgure n.2 Autostore mode the CS is pulled on Vcc with a 10k resistor ( always pulled up when the power in on!!! ) in onother datasheet of product similar ( nvram with RTC but not WITHOUT SPI interface) CY14B101KA at page 4 there is the same drow (figure2 autostore mode) but this thime WE is pulled on wcc with 10 k resistor and this provably is the true configuration!! on another cypress document the application note AN43593 on page 1 the drow FIgure 1 report a autostore configuration equals then CY14B101KA datasheet..! another question: we use single chip mode : the HOLD pin is pulled on vcc or gnd for work??? please inform me about the error ! we loss a lot of time for redrow our project!!! |
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这篇文章中的问题似乎已经通过赛普拉斯技术支持频道得到了解答。我在这里填写答案。
在SPI NVSRAM中的CS/PIN上拉: 芯片选择引脚(CS/)应在正常操作期间由控制器驱动。在上电时,控制器引脚在启动时可能是浮动的。在控制器启动时间大于NVSRAM启动时间(THSECHORE=20MS)的情况下,如果浮动控制器输出向引脚呈现低电平,则选择NVSRAM芯片。为了确保芯片没有被选择,建议CS/PIN被拔起。这将避免在这些条件下由于噪声引起的任何不希望的命令。 在并行NVSRAM上对W/PIN进行上拉: 与上述类似。如果连接到E//和CE/PIN的控制器引脚在上电期间浮动,并且如果NVSRAM被启动,则如果浮动引脚在E//和CE/PIN处呈现低逻辑电平,则会发生意外写入。这种不希望的写入会损坏SRAM位置,可能在第一位置(位置取决于浮动地址引脚中的电平)。为了防止这种情况,建议在W/PIN上拔出。 SPI上的保持/引脚上拉: 保持/引脚为低电平。因此,如果在应用程序中未使用此功能,则建议使用拖动,以确保保持未被断言。即使在使用保持特征的应用中,最好的做法是将这种拉起。 以上来自于百度翻译 以下为原文 The questions in this posting seem to have been answered through the Cypress tech support channel. I am posting answers here for completion. Pullup on CS/ pin in SPI nvSRAM: The Chip Select pin (CS/) should be driven by the controller during normal operation. During power up, it is possible that the controller pin would be floating when it is booting up. In case the controller boot up time is more than the nvSRAM boot up time (tHRECALL = 20ms), if the floating controller output presents a low to the pin, the nvSRAM chip is selected. To ensure that the chip is not selected, it is recommended that the CS/ pin is pulled up. This would avoid any undesired commands due to noise during these conditions. Pullup on WE/ pin in parallel nvSRAM: Similar to the above. If the controller pins connected to the WE/ and CE/ pins are floating during power up, and if nvSRAM is booted up, an unintended write can happen if the floating pins present low logic levels at WE/ and CE/ pins. Such an undesired write would corrupt the SRAM location, possibly in the first location (location depends on the levels in the floating address pins). To prevent this situation, a pull up is recommended on WE/ pin. Pullup on HOLD/ pin in SPI: HOLD/ pin is active low. Hence a pull up is recommended if this feature is not used in applications, to ensure Hold is not asserted. Even in application where Hold feature is used, it is a best practice to have this pull up in place. |
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