数据延迟时钟的原因可能是什么？如何减少它？

qizhong19920114写道：
我正在进行的设计使用了一个引脚的时钟，该引脚并非初始用作时钟源，因为电路板是固定的，所以我现在无法更改它。
时钟从该引脚（引脚chana_ri）输入，用作发送数据的状态机逻辑的时钟。
数据延迟的时钟现在约为16 ns，但我试图将其降低到10 ns以内。
我尝试了OFFSET约束，它将延迟从21ns降低到16ns。
但是我还能用什么来进一步降低延迟？
或者，如果这是最好的FPGA芯片（Spartan 3E）可以做的时钟到数据延迟（16 ns），那么导致延迟的原因是什么？
时钟到数据的延迟测量如何？
16 ns是非常大的。
请注意，OFFSET IN约束不会强制输入延迟为您指定的延迟。
它只是报告实施结果。
要更改延迟，您需要执行诸如使用DCM进行相移或使用IOB中的I / O延迟功能之类的操作。
RTFDS。
----------------------------是的，我这样做是为了谋生。



以下为原文

qizhong19920114 wrote:
The design I am doing uses a clock from a pin that is not initally intended to be a clock source and I can't change it now since the board is fixed. The clock is fed in from that pin (pin chana_ri) and is used as a clock for an state machine logic that sends out data. The clock to data delay is around 16 ns now, but I am trying to reduce it to within 10 ns. I tried OFFSET constraint which brings the delay down from 21ns to 16 ns. But what else can I use to bring the delay further down? Or if this is the best this FPGA chip (Spartan 3E) can do for the clock to data delay (16 ns), what is causing the delay this big?

Clock to data delay as measured how? 16 ns is ridiculously large.

Note that an OFFSET IN constraint doesn't force the input delay to be what you specify. It just reports the implementation result. To change the delay, you need to do things like use a DCM to phase shift, or use the I/O delay features in the IOB. RTFDS.
----------------------------Yes, I do this for a living.