为什么在verilog中添加与逻辑的其他部分无关的进程会影响输出？

>>但是，输出与我的观察略有不同。你需要更具体地了解你的预期和观察结果，以便可以做出更详细的反应，但一般来说观察系统可能会改变它的行为:-)特别是
在您的情况下，添加观察点可能会阻止综合工具进行一些优化并为合成输出添加更多逻辑。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

>> However, the output is slightly different from my observation.

you need to be more specific as to what you expected and observed so that a more detailed response can be made but in general observing a system may change its behavior :-)
Specifically in your case, it is possible that adding an observation point is preventing the synthesis tool making some optimizations and adding more logic to the synthesized output.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

嗨Muzaffer，
非常感谢您的回复。
我有点惊讶的是，添加一个观察点可以改变系统的行为bc我曾经是一个C程序员：p。
但我知道FPGA是非常不同的野兽。
“有可能添加一个观察点阻止综合工具进行一些优化，并为合成输出添加更多逻辑。”
这就是我认为可能导致问题的原因。
合成工具的工作方式对我来说一直是个谜。
我想知道如何防止或最小化由综合工具引起的这种不良影响。
谢谢
齐



以下为原文

Hi Muzaffer,
Thank you very much for your reply. I am kinda surprised that adding an observating point can change the behavior of the system bc I used to be a C programmer :p. But I know that FPGA is very different beast.

" it is possible that adding an observation point is preventing the synthesis tool making some optimizations and adding more logic to the synthesized output."

That is what I thought that could happen that causes the issue. The way synthesis tool works has always been a mystery for me. I would like to know how to prevent or minimize such undesirable influence causing by the synthesis tool.

Thanks

Qi