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我正在研究一种我喜欢Xilinx EVB KC705的设计。
我尝试使用LPC FMC连接。 LPC中的GTX处于四通道117，而与LPC连接的ref时钟是四通道116 ref clock 1（基于原理图）。在我的设计中，我需要两个116的ref时钟用于四通道117中的MGT3。然后在我的 设计我在比特流生成阶段有错误，它是： 设计没有完成路由，错误发生在两个ref时钟。 在这种情况下，我想知道KIntex 7 GTX是否可以使用相邻四边形的两个参考时钟？ 根据我的理解，我知道GTX可以使用相邻四极杆的参考时钟，但我不确定使用两个时钟是否可行。 提前致谢。 以上来自于谷歌翻译 以下为原文 I am working on a design whcih I amusing Xilinx EVB KC705. I try to use the LPC FMC connect. The GTX in LPC is in quad 117 while the ref clocks connect with LPC is in quad 116 ref clock 1 (based on schematic).In my design, I need both ref clock from quad 116 for the MGT3 in quad 117. Then in my design I have error in bitstream generation stage which is : design is not completed routed, the errors happen in two ref clocks. In this case, I wonder whether KIntex 7 GTX can use both two ref clocks from adjacent quad? Based on my understanding, I know GTX can use the ref clock from adjacent quad, but I am not sure whether using two clocks is feasible or not. Thanks in advance. 
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大家好，在我将两个ref时钟连接到CPLL和QPLL NORTHREFCLK之后，设计通过了比特流生成。所以我尝试通过经验和UG476.1确认以下理解。
当只需要一个参考时钟，即使时钟来自另一个四核，它仍然可以与CPLL和QPLL中的GTREFCLK_IN连接，正确？2。 当我需要两个参考时钟时，它们都来自另一个四核，我必须根据银行位置将它们连接到CPLL，QPLL中的NORTH或SOUTH CLK_IN，对吗？我的另一个问题是，如果时钟来自MGTREF_CLK0引脚 ，我是否必须在CPLL和QPLL中连接GTREFCLK0，或者我可以将它交换到GTREFCLK1？谢谢。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hello all, After I connect two ref clocks to both CPLL and QPLL NORTHREFCLK, then the design pass the bitstream generation. So I try to confirm following understanding from experience and from UG476. 1. WhenＩonly need one ref clock, even the clock come from another quad, it can still be connected with GTREFCLK_IN in CPLL and QPLL, correct? 2. When I need two ref clocks, both of them come from another quad, I have to connect them with NORTH or SOUTH CLK_IN in CPLL, QPLL, based on bank location, correct? Another question I have is, if the clock comes from MGTREF_CLK0 pin, do I have to connect with GTREFCLK0 in CPLL and QPLL, or I can swap it to GTREFCLK1? Thank you.View solution in original post |
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可以路由来自相邻四边形的两个REFCLK。
请尝试使用GT向导正确设置时钟。 -------------------------------------------------- ----------------------------别忘了回复，给予kudo并接受为解决方案--------- -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Both REFCLK's from adjacent quad can be routed. Please try to use GT wizard to setup the clocking properly.------------------------------------------------------------------------------ Don't forget to reply, give kudo and accept as solution ------------------------------------------------------------------------------ |
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嗨，
您是否可以共享您看到错误的设计，以便我可以查看错误的原因是什么？ 以上来自于谷歌翻译 以下为原文 Hi, Is it possible for you to share the design in which you see the error so taht i can have a look on what could be the reason for the error? |
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感谢您的回复。
在我的设计中，我手动实例化了QPLL。 我想知道，因为ref时钟来自相邻的四核，我应该把时钟驱动到GTNORTHREFCLK还是GTSOUTHREFCLK？基于芯片，时钟来自116银行，而GT在117银行，时钟低于GT，在 这种情况，我应该把时钟驱动到北方吗？谢谢。 以上来自于谷歌翻译 以下为原文 Thank you for reply. In my design, I instantiated the QPLL manually. I wonder since the ref clocks come from adjacent quad, should I driven the clock into the GTNORTHREFCLK or GTSOUTHREFCLK? Based on the chip, the clock come from 116 bank while the GT is in 117 bank, the clock is below of the GT, in this case, should I driven the clock to North? Thank you. |
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你好，
无需使用GMNORTHREFCLK来路由时钟。 您可以直接将时钟路由到四线以上的GTREFCLK0 / 1。 请参阅第页码中的图像。 以下用户指南中的42个：http：//www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf 还要分享完整的错误消息，这有助于我们进一步调查问题并了解您的使用情况。 谢谢， 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题？ ？ 如果没有，你应该在发布之前。 此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hello, No need to use GTNORTHREFCLK for routing the clock. You can directly route the clock to GTREFCLK0/1 from above quad. See the image in page no. 42 of the following user guide: http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf Also share the complete error message which helps us to investigate the issue further and understands your usage. Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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嗨pulim，非常感谢你愿意帮助我。
我正在努力研究是否可以修复它，因为我得到了一些提示。 如果我不能，我会告诉你，看看你是否可以进一步帮助我。 谢谢。 以上来自于谷歌翻译 以下为原文 Hi pulim, Thank you very much that you are willing to help me. I am working on that to see whether I can fix it since I get some hints. If I can't, I will pm you to see whether you can assist me further. Thank you. |
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嗨Vinay，在我的情况下，我需要两个ref时钟，所以我认为第45页的图2-8更接近我的情况。
我发布错误如下：路由设计[路线35-54]净：mgtclk_148_35未完全路由。[路线35-54]净：mgtclk_148_5未完全路由。[路线35-54]净：mgtclk_148_35未完全路由 。[Route 35-54] Net：mgtclk_148_5未完全路由。[Route 35-7]设计有2个不可路由的引脚，可能由放置问题引起。[Route 35-1]设计没有完全路由。 有2个网络未完全路由。写入比特流[Drc 23-20]规则违规（RTSTAT-2）部分路由网络 - 2net（s）部分路由。 问题网是mgtclk_148_5，mgtclk_148_35。[Vivado 12-1345]在DRC期间发现错误。 比特根没跑。 以上来自于谷歌翻译 以下为原文 Hi Vinay, In my cases, I need two ref clocks, so I think Figure 2-8 in Page 45 is more close to my cases. I post the errors as following: Route Design[Route 35-54] Net: mgtclk_148_35 is not completely routed. [Route 35-54] Net: mgtclk_148_5 is not completely routed. [Route 35-54] Net: mgtclk_148_35 is not completely routed. [Route 35-54] Net: mgtclk_148_5 is not completely routed. [Route 35-7] Design has 2 unroutable pins, potentially caused by placement issues. [Route 35-1] Design is not completely routed. There are 2 nets that are not completely routed. Write Bitstream[Drc 23-20] Rule violation (RTSTAT-2) Partially routed net - 2 net(s) are partially routed. The problem net(s) are mgtclk_148_5, mgtclk_148_35. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. |
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大家好，在我将两个ref时钟连接到CPLL和QPLL NORTHREFCLK之后，设计通过了比特流生成。所以我尝试通过经验和UG476.1确认以下理解。
当只需要一个参考时钟，即使时钟来自另一个四核，它仍然可以与CPLL和QPLL中的GTREFCLK_IN连接，正确？2。 当我需要两个参考时钟时，它们都来自另一个四核，我必须根据银行位置将它们连接到CPLL，QPLL中的NORTH或SOUTH CLK_IN，对吗？我的另一个问题是，如果时钟来自MGTREF_CLK0引脚 ，我是否必须在CPLL和QPLL中连接GTREFCLK0，或者我可以将它交换到GTREFCLK1？谢谢。 以上来自于谷歌翻译 以下为原文 Hello all, After I connect two ref clocks to both CPLL and QPLL NORTHREFCLK, then the design pass the bitstream generation. So I try to confirm following understanding from experience and from UG476. 1. WhenＩonly need one ref clock, even the clock come from another quad, it can still be connected with GTREFCLK_IN in CPLL and QPLL, correct? 2. When I need two ref clocks, both of them come from another quad, I have to connect them with NORTH or SOUTH CLK_IN in CPLL, QPLL, based on bank location, correct? Another question I have is, if the clock comes from MGTREF_CLK0 pin, do I have to connect with GTREFCLK0 in CPLL and QPLL, or I can swap it to GTREFCLK1? Thank you. |
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你好，
请参阅下面的查询答案。 是的 2.如果使用MGTREFCLK0和MGTREFCLK1驱动低于或高于四路的GT，则可以使用GT的GTREFCLK0和GTREFCLK1来路由时钟。 3.你为什么要交换？ 谢谢， 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题？ ？ 如果没有，你应该在发布之前。 此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hello, See below for answers to your queries. 1. Yes. 2. If you are using MGTREFCLK0 and MGTREFCLK1 for driving the below or upper quad GTs, then you can use GTREFCLK0 and GTREFCLK1 of GTs for routing the clock. 3. Why do you want to swap? Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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嗨Vinay，谢谢你的回复。
对于Q2，在GT中，有GTREFCLK0和GTREFCLK1，还有QPLLREFCLKIN。 我什么时候应该使用它们？对于Q3，我只是很好奇。谢谢。 以上来自于谷歌翻译 以下为原文 Hi Vinay, Thank you for reply. For Q2, in GT, there is GTREFCLK0 and GTREFCLK1, and also a QPLLREFCLKIN. When should I use them? For Q3, I am just curious. Thank you. |
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你好，
对于Q2，请参阅第页码中的端口说明。 UG476的第37和38页。 对于Q3，是的，你可以交换。 谢谢， 维奈 -------------------------------------------------- ------------------------------------------您是否尝试在Google中输入问题？ ？ 如果没有，你应该在发布之前。 此外，MARK这是一个答案，以防它有助于解决您的查询/问题。给予帮助您找到解决方案的帖子。 以上来自于谷歌翻译 以下为原文 Hello, For Q2, See ports description in page no. 37 and 38 of UG476. For Q3, yes, you can swap. Thanks, Vinay -------------------------------------------------------------------------------------------- Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution. |
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你好@ buddha1987，
请关闭此帖子。 --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hello @buddha1987, Please close this thread. --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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嗨Syed，我想我做到了。
或者我应该如何关闭线程？谢谢。 以上来自于谷歌翻译 以下为原文 Hi Syed, I think I did. Or how should I close the thread? Thanks. |
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嗨@ buddha1987，
我很抱歉，我错过了你已经将有用的帖子标记为“已接受的解决方案” 干杯， 赛义德 -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用，请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 Hi @buddha1987, I apologies, i have missed to see that you have already marked the helpful post as "Accepted Solution" Cheers, Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
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