如何计算异步FIFO深度和单独的时钟源

使用Coregen，我为独立时钟生成了一个FIFO，目标是分布式RAM（V7 2000T设备）。
输入和输出的数据都是84位宽。
写入数据在wr clk = 200 MHz的每4个时钟上连续写入。
当fifo不为空时，用rd clk = 50 MHz连续读出数据。
从模拟开始，在5次写入后，fifo空置为空。
如何正确计算深度？
最初，我的深度为16，所有人都在董事会工作。
然后进行实验，我改变了wr和rd时钟，使得它们来自单独的板载振荡器。
这导致了fifo溢出。
我将深度更新为128，然后再次运行。
如果有人可以告诉我发生了什么，以及这个FIFO设置是否可以可靠地处理来自不同来源的时钟，我真的很感激。
我打算有相同的来源，但想知道有什么限制。
问候，
标记



以下为原文

Using Coregen, I generated a FIFO for independent clocks targe ting Distributed RAM (V7 2000T device).

The data in and out are both 84 bits wide.

The write data is continuously written on every 4th clock of the wr clk = 200 MHz.

When fifo not empty, data is continuously read out with rd clk = 50 MHz.
From simulation, the fifo empty deasserts after 5 writes.

How do I correctly calculate the depth?

Initially, I had a depth of 16 and all worked on the board.
Then to experiment, I changed the wr and rd clocks such that they were derived from separate on-board oscillators. This resulted in a fifo overflow. I updated the depth to 128 and it’s working again.

I’d really appreciate if someone can enlighten me as to what’s transpiring and if this FIFO setup can reliably handle clocks from separate sources. I plan to have the same source but would like to know what are the limitations otherwise.

Regards,
Mark