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我需要创建一个需要通过一些启用进行门控的Diffenertial时钟。 我怎样才能做到这一点？ 我能做那样的事吗？ CLK_i0：OBUFDSport map（I => CLK100MHZ AND some_En，O => EP，OB => EN）; 最好的问候，弗雷德 以上来自于谷歌翻译 以下为原文 Hello, I have a need to create a Diffenertial clock that needs to be gated with some enable. How can I do that? can I do something like that? CLK_i0 : OBUFDS port map ( I => CLK100MHZ AND some_En, O => EP, OB => EN ); Best regards, Fred 
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你需要这个门控时钟是什么？
它只是用于转发出FPGA，还是你还需要在内部使用它？ 如果它只是转发，那么你可以在出路时完成，但不能直接控制OBUFDS。 转发时钟的正确方法是通过ODDR。 通常做时钟转发，将D1连接到1，D2连接到0; 在内部时钟的上升沿，D1被发送出去（因此为1），在内部时钟D2的下降沿被发送出去（因此为0）。 然后将ODDR的输出发送到OBUFDS。 要“关闭”此时钟，只需使用some_EN作为ODDR的D1输入; 当some_EN为0时，D1和D2都为0，这将发出一个常数0模式...... 您可能很重要的是，与您在OBUFDS中描述的相比，这将有一个额外的延迟时钟; 在你的实现中，some_EN的无效将立即对时钟进行门控（包括部分抑制当前的高脉冲）。 使用ODDR实现时，some_EN的无效将禁用下一个时钟脉冲。 按照你描述的方式完成，some_EN的无效将是时间关键的; 取决于它何时从高转变为低，几乎完全，部分或根本不会抑制当前时钟脉冲。 这可能会产生一个太短的脉冲，称为“欠幅脉冲”。 这很容易搞乱下游逻辑。 当some_EN从低转变为高时也会发生同样的情况 - 它可以部分地重新启用下一个时钟脉冲。 防止这种情况的唯一方法是确保some_EN仅在时钟周期的后半段改变状态 - 当输出时钟为0时，无论some_EN的状态如何 - 这在工具中很难确保......（ 特别是在ISE）。 如果您需要在FPGA内部进行时钟门控，那么您应该使用BUFGCE - 这是一个具有门控功能的时钟缓冲器，旨在实现无故障（和无时间）时钟门控。 Avrum 以上来自于谷歌翻译 以下为原文 What do you need this gated clock for? Is it just for forwarding out of the FPGA, or do you also need to use it internally? If it is just forwarding, then you can do it on the way out, but not by gating the OBUFDS directly. The proper way to forward a clock is through an ODDR. Normally to do clock forwarding, you tie D1 to 1 and D2 to 0; on the rising edge of the internal clock, D1 is sent out (hence a 1), on the falling edge of the internal clock D2 is sent out (hence a 0). The output of the ODDR would then be sent to an OBUFDS. To "gate" this clock, then just use your some_EN as the D1 input of the ODDR; when some_EN is 0, this both D1 and D2 will be 0, which will send out a constant 0 pattern... It may be important for you to know that this will have one clock additional latency compared to what you described with the OBUFDS; with your implementation, the deassertion of some_EN would immediately gate the clock (including partly supressing the current high pulse). With the ODDR implementation, the deassertion of some_EN would disable the next clock pulse. Done the way you described, the deassertion of some_EN would be timing critical; depending on exactly when it transitioned from high to low, it would almost completely, partly, or not at all supress the current clock pulse. This could generate a pulse that is too short, called a "runt" pulse. This can easily mess up downstream logic. The same can happen when the some_EN transitions from low to high - it could partly re-enable the next clock pulse. The only way to prevent this is to ensure that some_EN changes state only during the 2nd half of the clock period - when the outgoing clock would be 0 regardless of the state of some_EN - this is very hard to ensure in the tools... (particularly in ISE). If you need to do clock gating inside the FPGA, then you should use a BUFGCE - this is a clock buffer with gating capability, designed to allow glitchless (and runtless) clock gating. Avrum |
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这是什么设备？
或者您可以使用SelectIO向导的帮助来转发时钟。 谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。 以上来自于谷歌翻译 以下为原文 What device is this? Or you can use the help of SelectIO wizard to forward the clock.Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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对于外部信号的时钟门控，可以使用缓冲区OBUFTDS。
然而，如上所述，这不是转发时钟的正确方法，因为转发的时钟信号完整性可能不好。 谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。 以上来自于谷歌翻译 以下为原文 For clock gating of signals outside you can use the buffer OBUFTDS. However as said, this is not the correct way to forward the clock as the forwarded clock signal integrity might not be good.Thanks, Anirudh PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution. |
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@avrumw，
是的，它是转发它，它必须是LVDS。 问候，弗雷德 以上来自于谷歌翻译 以下为原文 @avrumw, Yes it is to forward it and it has to be LVDS. Regards, Fred |
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