从综合报告计算时间延迟的问题

我在vhdl中设计了一个模数（2n + 1）乘法器，带有2个设计--- 1个组合，即没有时钟和另一个流水线设计
组合 电路中的综合报告如下
最短期限：未找到路径
时钟前的最小输入到达时间：未找到路径
时钟后最大输出所需时间：未找到路径
最大组合路径延迟：43.684 ns
对于流水线设计，综合报告可以找到
最小周期：2.616 ns（最大频率：382.291 MHz）时钟前的最小输入到达时间：5.016ns时钟后的最大输出所需时间：4.092ns最大组合路径延迟：未找到路径
从理论上讲，我可以证明流水线设计的吞吐量（即每单位时间处理的位数）多于组合设计的吞吐量。但是如何从综合报告中得出相同的结论呢？
在流水线设计的综合报告中，没有找到组合路径延迟，这是非常清楚的，因为没有从没有时钟的输入到输出找到路径。但是我怎样才能计算出这个设计的延迟？
是否有任何计算需要在流水线设计中找到输出延迟输入....



以下为原文


I have designed a modulo (2n + 1) mul tiplier in vhdl with 2 design--- 1 combinational i.e without clock and another pipelined design
The synthesis report in combinational circuit is found as

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 43.684 ns




For the pipelined design, the synthesis report is found as

Minimum period: 2.616 ns (Maximum Frequency: 382.291 MHz)
Minimum input arrival time before clock: 5.016ns
Maximum output required time after clock: 4.092ns
Maximum combinational path delay: No path found


Theoretically I can prove that the throughput( i.e the number of bits processed per unit time) of the pipelined design is more that that of combinational design.But how can I conclude the same thing from the synthesis report??

In the synthesis report of the pipelined design, the combinational path delay is not found which is quite clear as no path is found from input to output which do not have a clock.But how can I calculate the delay in this design?

Is there any calculation need for finding input to output delay in pipelined designs....???