完善资料让更多小伙伴认识你，还能领取20积分哦， 立即完善>
3天内不再提示
德赢Vwin官网
论坛|
大家好，
我刚开始学习FPGA并试图弄清楚哪些FPGA引脚可以分配我的数据信号。 我正在使用FPGA Spartan 6封装TQG114器件LX9。 查看产品规格，有102个可用的用户I / O. 这是否意味着我可以使用102个引脚中的任何一个来分配我的数据信号？ 详细介绍每个IO引脚名称，如HSWAPEN，GCLK，GCLK_USERCCLK，VREF，SCP，AWAKE，DOUT_BUSY，CMPCLK_2，CMPMOSI_2，MOSI_CSI_B_MISO，CSO，GCLK_TRDY等。 一些Pin描述说您可以将引脚用作常规用户I / O，但有些则不然。 例如： GCLK：这些时钟引脚连接到全局时钟缓冲器。 当时钟不需要时，这些引脚成为常规用户I / O. VREF：这些是输入阈值电压引脚。 当不需要外部阈值电压时（每个存储区），它们将成为用户I / O. 当用作bank中的参考电压时，必须连接该bank中的所有VREF引脚。 所以我相信IO_GCLK和IO_VREF引脚可以用作普通用户IO，但其他用户呢？ 例如： SCP：暂停控制针SCP0-SCP7。 用于SUSPEND多针唤醒功能。 并且方向列显示它是“INPUT”。 谢谢 Krit S. 以上来自于谷歌翻译 以下为原文 Hi all, I just started learning FPGA and trying to figure out which FPGA pins I can assign my data signals to. I am using FPGA Spartan 6 Package TQG114 Device LX9. Looking at the Product Specification, there are 102 available user I/Os. Does that mean I can use any of the 102 pins to assign my data signals to? Going into more details on each IO pins name such as HSWAPEN, GCLK, GCLK_USERCCLK, VREF, SCP, AWAKE, DOUT_BUSY, CMPCLK_2, CMPMOSI_2, MOSI_CSI_B_MISO, CSO, GCLK_TRDY, etc. Some of the Pin description said you can use the pins as regular user I/Os but some don't. For example on: GCLK: These clock pins connect to global clock buffers. These pins become regular user I/Os when not needed for clocks. VREF: These are input threshold voltage pins. They become user I/Os when an external threshold voltage is not needed (per bank). When used as a reference voltage within a bank, all VREF pins within that bank must be connected. So I believe IO_GCLK and IO_VREF pins can be used as regular user IO but what about the others? For example: SCP: Suspend control pins SCP0-SCP7. Used for SUSPEND multi-pin wakeup feature. and the direction column shows that it's for "INPUT". Thank you Krit S. 
0
|
|
相关推荐
3个回答
|
|
|
听起来你还有一些阅读要做。
顾名思义，任何以“IO”开头的引脚都可用于设计的标准输入或输出。 然而，这些引脚中的许多引脚都是多功能的，因此它们是否可用于您的特定设计取决于您是否需要这些引脚用于其备用功能。 Vref就是一例。 这些引脚必须用于在任何存储区中提供参考电压，输入需要像SSTL这样的参考电压。 配置引脚是另一个。 在某些情况下，配置可能需要一些引脚，如SPI串行，或者使用selectMAP的几十个引脚。 对于像您这样的小型设备，使用SPI或可能的4位宽QSPI进行配置通常是有意义的，以限制使用的引脚数量。 配置后，即使这些引脚可以重新利用，但这通常会产生系统级问题。 所以大多数时候你会考虑专用于配置的引脚。 Spartan 6上的模式选择引脚也是如此。通常使用板级电阻上拉或下拉，但配置完成后，它们可用作I / O. 最简单的方法是将它们用作输出，因为FPGA在需要选择配置模式时不会驱动它们。 在严格的设计中，您可以将它们用作输入，但是您需要确保输入源在配置完成之前不驱动它们。 有关Spartan-6 FPGA SelectIO资源用户指南和Spartan-6 FPGA配置用户指南的更多信息。 - Gabor 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 It sounds like you still have some reading to do. As the name implies, any pin starting with "IO" can be used for standard input or output from your design. However many of these pins are multifunction, so whether they are usable in your particular design depends on whether you need these pins for their alternate function. Vref is one case. These pins must be used to supply reference voltage in any bank with inputs requiring a reference like SSTL. Configuration pins are another. Configuration can take a handful of pins in some cases like SPI serial, or dozens of pins with selectMAP. For a small device like yours, it generally makes sense to use SPI or possibly 4-bit-wide QSPI for configuration to limit the number of pins used. After configuration even these pins can be repurposed, but that often creates system-level issues. So most of the time you would consider the pins dedicated to configuration. The same is true of the mode select pins on Spartan 6. Typically they are pulled up or down with a board level resistor, but after configuration they can be used as I/O. It's easiest to use them as outputs, since the FPGA won't ever drive them while they're needed to select the configuration mode. In a tight design, you could use them as inputs, but you'd need to make sure the input source isn't driving them before configuration completes. More information in Spartan-6 FPGA SelectIO Resources User Guide and Spartan-6 FPGA Configuration User Guide. -- GaborView solution in original post |
|
|
|
|
|
以下是包装和引脚分布产品规格的pdf链接
https://www.xilinx.com/support/documentation/user_guides/ug385.pdf 以上来自于谷歌翻译 以下为原文 Here is the pdf link for the packaging and pinouts product specification https://www.xilinx.com/support/documentation/user_guides/ug385.pdf |
|
|
|
|
|
听起来你还有一些阅读要做。
顾名思义，任何以“IO”开头的引脚都可用于设计的标准输入或输出。 然而，这些引脚中的许多引脚都是多功能的，因此它们是否可用于您的特定设计取决于您是否需要这些引脚用于其备用功能。 Vref就是一例。 这些引脚必须用于在任何存储区中提供参考电压，输入需要像SSTL这样的参考电压。 配置引脚是另一个。 在某些情况下，配置可能需要一些引脚，如SPI串行，或者使用selectMAP的几十个引脚。 对于像您这样的小型设备，使用SPI或可能的4位宽QSPI进行配置通常是有意义的，以限制使用的引脚数量。 配置后，即使这些引脚可以重新利用，但这通常会产生系统级问题。 所以大多数时候你会考虑专用于配置的引脚。 Spartan 6上的模式选择引脚也是如此。通常使用板级电阻上拉或下拉，但配置完成后，它们可用作I / O. 最简单的方法是将它们用作输出，因为FPGA在需要选择配置模式时不会驱动它们。 在严格的设计中，您可以将它们用作输入，但是您需要确保输入源在配置完成之前不驱动它们。 有关Spartan-6 FPGA SelectIO资源用户指南和Spartan-6 FPGA配置用户指南的更多信息。 - Gabor 以上来自于谷歌翻译 以下为原文 It sounds like you still have some reading to do. As the name implies, any pin starting with "IO" can be used for standard input or output from your design. However many of these pins are multifunction, so whether they are usable in your particular design depends on whether you need these pins for their alternate function. Vref is one case. These pins must be used to supply reference voltage in any bank with inputs requiring a reference like SSTL. Configuration pins are another. Configuration can take a handful of pins in some cases like SPI serial, or dozens of pins with selectMAP. For a small device like yours, it generally makes sense to use SPI or possibly 4-bit-wide QSPI for configuration to limit the number of pins used. After configuration even these pins can be repurposed, but that often creates system-level issues. So most of the time you would consider the pins dedicated to configuration. The same is true of the mode select pins on Spartan 6. Typically they are pulled up or down with a board level resistor, but after configuration they can be used as I/O. It's easiest to use them as outputs, since the FPGA won't ever drive them while they're needed to select the configuration mode. In a tight design, you could use them as inputs, but you'd need to make sure the input source isn't driving them before configuration completes. More information in Spartan-6 FPGA SelectIO Resources User Guide and Spartan-6 FPGA Configuration User Guide. -- Gabor |
|
|
|
|
只有小组成员才能发言，加入小组>>
2420 浏览 7 评论
2823 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办？
2294 浏览 9 评论
3374 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区？
2461 浏览 15 评论
有输入，但是LVDS_25的FPGA内部接收不到数据，为什么？
1174浏览 1评论
请问vc707的电源线是如何连接的，我这边可能出现了缺失元件的情况导致无法供电
587浏览 1评论
求一块XILINX开发板KC705，VC707，KC105和KCU1500
451浏览 1评论
2005浏览 0评论
731浏览 0评论
/7 
关注我们的微信
下载发烧友APP
德赢Vwin官网 观察
版权所有 © 湖南华秋数字科技有限公司
德赢Vwin官网 （电路图） 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证：合字B2-20210191
工商网监
湘ICP备2023018690号
2001
评论
淘帖
2672
