System Generator是MatLab到RTL的转换吗

根据我的理解，System Generator是MatLab到RTL的转换，因此不包括Vivado的优化过程。
问题1--是真的。
1，Sysgen反手使用IP核，用于某些块，即FFT，FIR等。
2.黑盒子 - 您可以使用自己的RTL，Xilinx IP在sysgen中导入
3. Mcode - 它使用matlab代码转换为RTL。
应该将mcode写入sysgen用户指南中给出的syntex。
sysgen不支持所有matlab syntex。
例如，不支持循环
4.直接支持一些simulink块。
在simulink工作区右键单击添加块将为您提供支持列表
5.检查sysgen中的索引库，了解sysgen中的所有可用块。
确实，Vivado中的优化将大大改变系统描述，而系统描述不会向后兼容系统生成器模型。
问题2 - 这是真的吗？
[]不是不是真的。
检查sysgen中的可用编译选项
如果1和2都是真的，那么暗示是System Generator模型旁边的点???
问题3 - 是真的
请讨论。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

In my understanding, System Generator is a MatLab conversion to RTL and does not therefore include the optimization processes of the Vivado.

Question 1-- is that true.
1, Sysgen use IP cores in backhand for some blocks i.e. FFT , FIR etc.
2. Black box - you can use your own RTL, Xilinx IP to import in sysgen
3. Mcode - its uses matlab code to convert into RTL. the mcode should be written into syntex given in sysgen user guide . the all matlab syntex not supported by sysgen. For example loops not supported
4. some simulink block directly supported . on simulink workspace right click add block will give you supported list
5. Check the index library in sysgen for all the available bocks in sysgen .

It true, the optimization in Vivado would substantially change the system description which would not be backwards compatible to the System Generator Model.

Question 2 -- is that true?
[] no its not true. check available compilation options in sysgen
If 1 and 2 are both true the implication is the System Generator model is beside point ???

Question 3 -- is that true

Please discuss.

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Give kudos in case a post in case it guided to the solution.View solution in original post

麦克风，
系统生成器使用以VHDL编写的IP块（主要是一些verilog）。
没有转换。
所有VHDL和verilog都被合成，放置和路由。
该过程包含许多步骤，包括优化（删除未使用的逻辑，逻辑减少/优化等）。
HLS中的C ++导致verilog源，然后通过完全相同的综合，位置和路由。
我们的保证是结果在两种流程中都是功能相同的。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Mike,

System generator uses IP blocks which are written in VHDL (mostly, some verilog as well). No conversion.

All VHDL and verilog gets synthesized, placed, and routed. That process has many steps, including optimization (removal of not used logic, logic reduction/optimization, etc.).

C++ in HLS results in verilog source, which then goes through exactly the same synthesis, place, and route.

Our guarantee is that the result is functionally equivalent in either flow.


Austin Lesea
Principal Engineer
Xilinx San Jose

根据我的理解，System Generator是MatLab到RTL的转换，因此不包括Vivado的优化过程。
问题1--是真的。
1，Sysgen反手使用IP核，用于某些块，即FFT，FIR等。
2.黑盒子 - 您可以使用自己的RTL，Xilinx IP在sysgen中导入
3. Mcode - 它使用matlab代码转换为RTL。
应该将mcode写入sysgen用户指南中给出的syntex。
sysgen不支持所有matlab syntex。
例如，不支持循环
4.直接支持一些simulink块。
在simulink工作区右键单击添加块将为您提供支持列表
5.检查sysgen中的索引库，了解sysgen中的所有可用块。
确实，Vivado中的优化将大大改变系统描述，而系统描述不会向后兼容系统生成器模型。
问题2 - 这是真的吗？
[]不是不是真的。
检查sysgen中的可用编译选项
如果1和2都是真的，那么暗示是System Generator模型旁边的点???
问题3 - 是真的
请讨论。
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

In my understanding, System Generator is a MatLab conversion to RTL and does not therefore include the optimization processes of the Vivado.

Question 1-- is that true.
1, Sysgen use IP cores in backhand for some blocks i.e. FFT , FIR etc.
2. Black box - you can use your own RTL, Xilinx IP to import in sysgen
3. Mcode - its uses matlab code to convert into RTL. the mcode should be written into syntex given in sysgen user guide . the all matlab syntex not supported by sysgen. For example loops not supported
4. some simulink block directly supported . on simulink workspace right click add block will give you supported list
5. Check the index library in sysgen for all the available bocks in sysgen .

It true, the optimization in Vivado would substantially change the system description which would not be backwards compatible to the System Generator Model.

Question 2 -- is that true?
[] no its not true. check available compilation options in sysgen
If 1 and 2 are both true the implication is the System Generator model is beside point ???

Question 3 -- is that true

Please discuss.

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

谢谢，详细解答非常有帮助。
迈克W



以下为原文

Thank you, the detailed answer is very helpful.

Mike W

谢谢你的回答说这个问题可以解决，这很好。
问题的第二部分涉及变革问题。
如果您通过控制语句（例如展开和管道）优化了c ++代码，那么这是c ++设计的一个组成部分。
您的回答清楚地表明，无论哪种方式都可以实现相同的结果。
那么优化是System Generator设计的一部分，还是第二层信息？
迈克W



以下为原文

Thank you that answer says the problem can be solved either way, which is good. The second part of the question addressed the issue of changes.

If you have optimized c++ code by control statements such as unroll and pipeline, that is an integral part of the c++ design.

Your answer makes it clear that the same result can be achieved either way. Is the optimization then a part of the System Generator design, or is it a second layer of information?

Mike W