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我已经把由收发器和触发器组成的togethera电路允许我通过8位GPIO总线将Raspberry Pi连接到5v逻辑1mhz 8位计算机。 我可以从复古计算机读取/写入，但是由于Raspberry Pi限制和非常紧张的时序余量，我在1000万次写入中遇到大约5个错误。 为了解决这个问题，我可以添加更多芯片并通过硬件做更多工作，这将使设计复杂化，或者我可以在CPLD上完成所有工作，我的朋友推荐给我他的XC9500XL，我需要学习Verilog。 在我开始之前，我遇到的一个问题是：我能够使用此CPLD创建收发器吗？ 我需要能够在两个方向上驱动总线以进行读/写。 我也正在读Samir Palnitkar的“Verilog HDL”第二版，所以任何适用于我的项目的阅读建议都将受到赞赏。 提前谢谢了！ 安东尼 以上来自于谷歌翻译 以下为原文 Hello, I've put together a circuit consisting of transceivers and flip-flops that allows me to interface a Raspberry Pi to a 5v-logic 1mhz 8-bit computer via an 8-bit GPIO bus. I am able to read/write from/to the retro computer but I am experiencing approximately 5 errors out of 10 million writes no matter what I do due to Raspberry Pi limitations and very tight timing margins. To fix this I can add more chips and do much more via hardware which will considerably complicate the design or I can do it all on a CPLD, and my friend recommended and gave me his XC9500XL which means I need to learn Verilog. One question I have before I go ahead is : am I able to create a transceiver using this CPLD? I need to be able to drive the bus in both directions for read/write purposes. I'm also reading the book "Verilog HDL" 2nd Ed by Samir Palnitkar so any additional reading recommendations applicable to my project would be appreciated. Many thanks in advance! Anthony 
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老实说，我要转储XC9500XL并购买Arduino或同等的微控制器套件。
XC9500XL很古老，它需要旧工具来编程（ISE 11），它还需要一个合适的编程器（Xilinx官方版本超过200美元）。 毕竟，它甚至不是5V芯片（仅3.3V）。 AVR（在Arduino上使用）将能够在5V时对8位并行总线进行bit-bang，具有非常精确的时序（如果您对代码非常小心，则周期精确），另一方面它 可以说I2C或UART（Raspberry Pi可以理解）。 因为它有一个内置的引导程序，你甚至不需要程序员。 以上来自于谷歌翻译 以下为原文 Honestly, I'd dump the XC9500XL and buy an Arduino or equivalent microcontroller kit. The XC9500XL is ancient, it requires old tools to program (ISE 11), and it also requires a proper programmer (the official Xilinx one is over $200). And, after all that, it's not even a 5V chip (only 3.3V). An AVR (as used on the Arduino) will be able to bit-bang an 8-bit parallel bus at 5V with pretty accurate timing (cycle-accurate, if you're very careful with the code), and on the other end it can talk I2C or UART (which the Raspberry Pi can understand). Because it's got a built-in bootloader you don't even need a programmer. |
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对不起，我的意思是XC9500支持3.3和5v，*不是XL版本;
不幸的是，我不再能够编辑OP。 我需要纳秒级别的响应/时序，所以Arduino根本不会削减它。 只要工作正常，我也不在乎工具集是否老旧; 锤子，钉子，锯子......等等都要老了，但它们仍然适合这项工作。 所有较新的CPLD都没有3.3 / 5伏特，所以对于我的目的，XC9500似乎符合要求，我只需要知道它是否能够合成收发器模块。 以上来自于谷歌翻译 以下为原文 Sorry, I meant XC9500 which has 3.3 and 5v support, *not* the XL version; unfortunately I am no longer able to edit the OP. I require nanosecond level response/timings so an Arduino simply will not cut it. I also don't care if the toolset is old so long as it works; hammers, nails, saws, etc... are much older but they're still perfect for the job. None of the newer CPLDs are 3.3/5 volt capable so for my purposes the XC9500 seems to fit the bill, I just need to know if it's capable of synthesizing a transceiver module. |
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@anthonypaulo取决于“收发器”的含义。
它能够做一些非常简单的事情（例如，一个SPI到并行转换，因为它基本上是一个移位寄存器） - 但可能不是很多。 XC9500并不是一款功能强大的芯片。 至于工具集的工作 - 好吧，只要你有Windows XP或更早版本，它可能会工作。 我不会指望在任何新的操作系统上工作的工具。 我对纳秒要求感到惊讶; 几纳秒意味着一个几百Mhz的时钟，这对于5V硬件来说是非常令人印象深刻的。 以上来自于谷歌翻译 以下为原文 @anthonypaulo Depends on what you mean by a "transceiver". It'll be able to do something very simple (eg. an SPI to parallel conversion, since that's basically a shift register) - but probably not much else. The XC9500 is not exactly a powerful chip. As for the toolset working - well, as long as you've got Windows XP or earlier, it'll probably work. I wouldn't count on the tools working on any newer OS. I'm surprised about the nanosecond requirement; a few nanoseconds implies a clock on the order of a few hundred Mhz, which is seriously impressive for 5V hardware. |
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纳秒要求是因为我有一个狭窄的25ns窗口，可以将我的数据放在总线上，否则它将无法工作。我会检查工具是否在较新的Windows上运行，如果不是，我将使用VM
。 以上来自于谷歌翻译 以下为原文 The nanosecond requirement is because I have a narrow 25ns window in which to place my data on the bus or else it won't work. I'll check to see if the tools run on newer Windows, if not I'll use a VM. |
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如果您正在使用1MHz的反向计算机，这意味着您的时钟周期为1000ns，时钟高电平时间为500ns，并且您通常需要大约400ns左右才能在CPU读取周期内将数据放在总线上。我做了一个
使用XC9500XL（XC9572XL）芯片与Acorn Electron和BBC Micro计算机上的数据总线连接的一系列逆向计算项目，它们的工作非常好。 以上来自于谷歌翻译 以下为原文 If you're working with a 1MHz retrocomputer, that means your clock period is 1000ns, the clock high time is 500ns, and you generally have around 400ns or so to place your data on the bus during a CPU read cycle. I've done a bunch of retrocomputing projects using XC9500XL (XC9572XL) chips to interface with the data bus on Acorn Electron and BBC Micro computers, and they work very nicely. |
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不幸的是，我的复古电脑并不宽容;
Apple IIe的写作机会非常紧密。 以上来自于谷歌翻译 以下为原文 Unfortunately my retro computer is not as forgiving; the Apple IIe has a very tight window of opportunity for writes. |
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你有项目链接吗？
很想看看你做了什么。 以上来自于谷歌翻译 以下为原文 Do you have a link to your projects? Would love to see what you’ve done. |
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绝对！
http://github.com/google/myelin-acorn-electron-hardware 这是一个很好的演示如何使用XC9572XL与6502的总线接口： https://github.com/google/myelin-acorn-electron-hardware/tree/master/serial_sd_adapter 如果Apple II的时间要求远远超过BBC Micro，我会感到惊讶; 他们使用相同的CPU，而Apple II以一半的速度运行（1MHz与BBC的2MHz相比）。当时的存储器的访问时间大约为150ns。 你能仔细检查一下你的计算吗？ 我忘了在我的另一篇文章中提到 - 你可能已经在你的帖子和我的帖子之间已经知道了这一点，但XC9500XL得到了ISE 14.7的支持。 ISE 14.7在Windows 10上非常崩溃，但在Linux上工作正常，并且Windows有一种解决方法可以重命名一些DLL。 我看到Xilinx刚刚发布了适用于Windows 10的ISE 14.7的VM版本（带有ISE的Red Hat Linux安装，捆绑为VirtualBox VM），虽然它被标记为“仅Spartan-6”，所以我不确定它是否支持 CPLD也是如此。 以上来自于谷歌翻译 以下为原文 Absolutely! http://github.com/google/myelin-acorn-electron-hardware This one is a good demonstration of how to use an XC9572XL to interface with the 6502's bus: https://github.com/google/myelin-acorn-electron-hardware/tree/master/serial_sd_adapter I'd be surprised if the Apple II's timing requirements were much tighter than the BBC Micro; they use the same CPU, and the Apple II runs at half the speed (1MHz compared to the BBC's 2MHz). Memory in those days had access times on the order of 150ns. Can you double check your calculations? I forgot to mention in my other post -- you've probably figured this out already in the months between your post and mine, but the XC9500XL is supported just fine by ISE 14.7. ISE 14.7 is very crashy on Windows 10, but works fine on Linux, and there's a workaround for Windows to do with renaming some DLLs. I see Xilinx just released a VM version of ISE 14.7 for Windows 10 (a Red Hat Linux installation with ISE, bundled as a VirtualBox VM), although it's marked as "Spartan-6 only", so I'm not sure if it supports the CPLDs as well. |
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我已多次阅读被认为是IIe的权威技术圣经，是的，我敢肯定;
IIe将一个周期分成一个阶段，在该阶段它可以进行读取和写入阶段。 由于时序相关的问题，我们需要避免外围总线上的colllisions，写入窗口非常紧张。 这是非常特别的II.I.安装了ISE webpack并找到了你描述的问题并在windows 10上应用了dll修复。我现在正在教自己verilog但是有点困难创建一个双向组件到 更换我的收发器; 我最终会得到它，虽然我希望转换的东西可以合成。我今晚回家时会查看你的链接！ 以上来自于谷歌翻译 以下为原文 I’ve read what is considered to be the definitive technical bible on the IIe many times over and yes, I’m sure; the IIe splits a cycle into a phase where it can do a read and a phase for writes. Due to timing related issues where we need to avoid colllisions on the peripheral bus the write window is really tight. This is really particular the the II’s. I installed the ISE webpack and found the issues you described and applied the dll fixes on windows 10. I’m currently teaching myself verilog but having a bit of a hard time creating a bi-directional component to replace my transceiver; I’ll get it eventually, though I wish the trans stuff could be synthesized. I’ll check out your links when I get home tonight! |
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我已经阅读了Apple II系列的一些内容，我想我知道你在谈论什么。
您是否尝试使用扩展卡进行DMA？ 如果你没有做DMA，你可能只需要满足非常的内存时序要求 - 读取，在PHI0的下降沿之前驱动数据总线大约100ns（在2MHz IIe上给你150ns），以及写入，读取 地址和数据总线在PHI0时钟的下降沿。 如果您正在进行DMA，那么定时看起来并不难以与CPLD相遇。更大的问题是避免总线冲突，因为CPLD对于系统的其余部分来说太快了:) 如果您可以访问7MHz时钟（143 ns周期），那么您应该能够完成所有任务，并保持良好状态。 如果您愿意使用VHDL而不是Verilog，我可以提供帮助，但我是一个完整的Verilog初学者，我很害怕！ 以上来自于谷歌翻译 以下为原文 I've read up a little on the Apple II series and I think I see what you're talking about. Are you trying to do DMA from an expansion card? If you're not doing DMA, you probably just need to meet ordinary memory timing requirements -- for reads, drive the data bus by ~100ns before the falling edge of PHI0 (which gives you 150ns on a 2MHz IIe), and for writes, read the address and data bus on a falling edge of the PHI0 clock. If you're doing DMA, the timings don't look too difficult to meet with a CPLD. The bigger problem is going to be avoiding bus conflicts because the CPLD will be too fast for the rest of the system :) If you have access to the 7MHz clock (143 ns period), you should be able to time everything off that and be fine. If you're open to using VHDL instead of Verilog, I can help, but I'm a complete Verilog beginner, I'm afraid! |
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哇这真的很酷！
你一个人在做这个吗？ 我认为这是一个入门套件，但后来我看到了串行卡文本; 你在哪里制作了电路板？ 另外，我自己也有亲微，你如何找到使用它？ 非常好！ 以上来自于谷歌翻译 以下为原文 Wow this is really cool! Did you work on this alone? I thought it was a Starter kit but then I saw the serial card text; where did you have the board made? Also, I have the pro micro myself, how do you find using it? Really nice! |
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是的！
在third_party文件夹之外的那个repo中的所有内容都是我自己的工作。 我将大部分PCB设计发送到Seeed，其余部分转到OSHPark（小型和4层）。我喜欢Pro Micro - 你可以使用Arduino工具链和库，USB支持很简单 。 一个非常好的接口板。 以上来自于谷歌翻译 以下为原文 Yep! Everything in that repo outside the third_party folder is my own work. I send most of my PCB designs to Seeed these days, and the rest go to OSHPark (small ones and 4 layer ones). I like the Pro Micro — you get to use the Arduino toolchain and libraries, and USB support is trivial with it. A really nice interface board. |
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