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我对Xilinx板上的RAM有疑问。 我正在寻找电路板上给定Block RAM的VHDL描述,在那里我可以直接将内存初始化文件的链接写入VHDL代码。 上次我使用Altera板时,我可以写下这样的东西: 开始 dmem:altsyncram 通用地图(width_a => 233, widthad_a => 7, width_b => 233, widthad_b => 7, init_file =>“data_mem.mif”) 端口映射(address_a => debug_addr, data_a =>(232 downto 0 =>'0'), wren_a =>'0', q_a => debug_out, clock0 => clk, address_b => dmem_addr, data_b => dmem_in, wren_b => dmem_we, q_b => dmem_out, clock1 => clk); 如您所见,有一个* .mif文件的链接,其中包含内存初始化。 还有其他泛型选择adressline和输入/输出大小。 我的问题是:XIlinx包中有类似的东西吗? 我在库中找到了一些东西(例如RAMB16BWE_S18_S18),但是你必须将整个内存初始化写入VHDL文件本身。 实际上我需要一个带有两个地址线和两个输出以及一般宽度(可能在22到42位之间)的RAM / ROM ...... 感谢帮助 以上来自于谷歌翻译 以下为原文 Hi everyone I have a quesion about RAMs on Xilinx Boards. I'm looking for a VHDL description for a given Block RAM on the board, where I can write a link to a Memory Init File directly into the VHDL code. Last time I worked with an Altera board, where I could write something like this: begin dmem : altsyncram generic map ( width_a => 233, widthad_a => 7, width_b => 233, widthad_b => 7, init_file => "data_mem.mif" ) port map ( address_a => debug_addr, data_a => (232 downto 0 => '0'), wren_a => '0', q_a => debug_out, clock0 => clk, address_b => dmem_addr, data_b => dmem_in, wren_b => dmem_we, q_b => dmem_out, clock1 => clk ); As you can see, there is a link to a *.mif file, that contains the memory initialisation. Also there are other generics to choose the adressline and input/output size. My question is: Is there something simular in the XIlinx package? I found something in the library (e.g. RAMB16BWE_S18_S18), but there you have to write the whole memory initialisation into the VHDL file itself. Actually I need a RAM/ROM with two address lines and two outputs and a generic width(maybe between 22 and 42 bits)... Thanks for help |
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2个回答
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当您从ISE包的Core生成器生成RAM / ROM时,它会建议您选择内存初始化文件.coe。
对于第二个问题,您可以在xilinx FPGA中使用双端口ram驻留 FPGA怪胎 以上来自于谷歌翻译 以下为原文 When u generate RAM/ROM from Core generator of ISE package, it propmts you to select the memory initialization file .coe. For your second question, you can use dual port ram resides in xilinx FPGA FPGA freak |
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是的,我发现核心的所有这些...除了通用宽度(我可以选择使用通用数字而不是精确的位数?)....
但这个核心是唯一的方式...... Imho它是这种简单初始化的超大资源;) 以上来自于谷歌翻译 以下为原文 Yeah, i found all this in the core gen....except of the generic width (where exactly can I choose to use a generic number instead of an exact number of bits?).... But is this core gen the only way... Imho it is a oversized resource for such a simple initialisation ;) |
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